Table of works
Frequent tags in this search: processor:4 0.5v:1 13-34:1 16-bit:1 4.18pj/cycle:1 accelerator:1 ace:1 analysis:1 bit:1 booth-value-confined:1 bulk:1 cmos:1 computing:1 contiguity-aware:1 contribution:1 edge-ai:1 estimation:1 featuring:1 ff:1 mapping:1 near-memory:1 operation:1 rate:1 reliability:1 risc:1 scaling:1 ser:1 soft-error:1 sram:1 technology:1
4 publications are found. : URL for this page. : HTML
| Author (author) | Title (title) | Journal/Conference | Volume / Number | Pages (pages) | Published date | Impact factor / Acceptance | File | |
|---|---|---|---|---|---|---|---|---|
| International Conference |
, , , , , , , , , M. Hashimoto |
A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping |
Technical Digest of Asian Solid-State Circuits Conference (A-SSCC) | October 2024 |
pdf | |||
| International Conference |
|
Processor SER Estimation with ACE Bit Analysis |
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) | September 2021 |
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| International Conference |
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto |
Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology |
IEEE Nuclear and Space Radiation Effects Conference (NSREC) | July 2013 |
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| International Conference |
D. Kuroda, H. Fuketa, M. Hashimoto, T. Onoye |
A 16-Bit RISC Processor with 4.18pJ/cycle at 0.5V Operation |
Proceedings of IEEE COOL Chips | 190 |
April 2010 |
145.pdf |