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論文誌

[1] J. Chen, H. Kando, T. Kanamoto, C. Zhuo, and M. Hashimoto, "A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions," IEEE Transactions on Components, Packaging and Manufacturing Technology, volume 9, number 9, pages 1669--1679, September 2019. [pdf]

[2] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, "Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3474-3480, December 2008. [113.pdf]

国際会議

[1] L. Zhang, J. Liu, H. Zhu, C-K Cheng, and M. Hashimoto, "High Performance Current-Mode Differential Logic," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 720--725, January 2008. [98.pdf]

[2] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and Chung-Kuan Cheng, "Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 869--872, September 2007. [91.pdf]