この検索内の頻出タグ: operation^:4 analysis^:2 0.3v^:1 0.5v^:1 0.8-v^:1 110-na^:1 16-bit^:1 4.18pj/cycle^:1 bulk^:1 characterization^:1 chip^:1 circuit^:1 cmos^:1 considering^:1 current^:1 interdependency^:1 load^:1 mcu^:1 mode^:1 model^:1 multi-core^:1 neutron-induced^:1 pdn^:1 processor^:1 rate^:1 reference^:1 risc^:1 seu^:1 sotb^:1 srams^:1

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論文誌

[1] J. Chen, H. Kando, T. Kanamoto, C. Zhuo, and M. Hashimoto, "A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions," IEEE Transactions on Components, Packaging and Manufacturing Technology, volume 9, number 9, pages 1669--1679, September 2019. [pdf]

[2] I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, "A 0.8-V 110-nA CMOS Current Reference Circuit Using Subthreshold Operation," IEICE Electronics Express (ELEX), volume 10, number 4, March 2013. [182.pdf]

国際会議

[1] S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, "Neutron-Induced SEU and MCU Rate Characterization and Analysis of SOTB and Bulk SRAMs at 0.3V Operation," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.

[2] D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, "A 16-Bit RISC Processor with 4.18pJ/cycle at 0.5V Operation," Proceedings of IEEE COOL Chips, page 190, April 2010. [145.pdf]