List of works
この検索内の頻出タグ: rate:8 error:5 neutron-induced:4 soft:4 bulk:3 ff:3 sram:3 chip-level:2 circuit:2 combinational:2 estimation:2 gpu:2 learning:2 machine:2 0.3v:1 0.5:1 1.0v:1 analysis:1 analyzing:1 application-level:1 characterization:1 characterizing:1 cmos:1 constructing:1 contribution:1 contributions:1 experiment:1 fd-soi:1 impacts:1 invited:1
- 論文誌
- [1] W. Liao and M. Hashimoto, "Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate," IEICE Trans. on Electronics, volume E102-C, number 4, pages 296--302, April 2019. [pdf]
- 国際会議
- [1] K. Ito, H. Itsuji, T. Uezono, T. Toba, M. Itoh, and M. Hashimoto, "Constructing Application-Level GPU Error Rate Model with Neutron Irradiation Experiment," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022.
- [2] K. Ito, W. Liao, M. Hashimoto, J. Kuroda, S. Manabe, Y. Watanabe, S. Abe, M. Harada, K. Oikawa, and Y. Miyake, "Characterizing Neutron-Induced SDC Rate of Matrix Multiplication in Tesla P4 GPU," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2019.
- [3] M. Hashimoto, W. Liao, and S. Hirokawa, "Soft Error Rate Estimation with TCAD and Machine Learning (Invited)," Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2017. [pdf]
- [4] W. Liao, S. Hirokawa, R. Harada, and M. Hashimoto, "Contributions of SRAM, FF and Combinational Circuit to Chip-Level Neutron-Induced Soft Error Rate -- Bulk vs. FD-SOI at 0.5 and 1.0V --," Proceedings of International NEWCAS Conference, pages 33-37, June 2017. [pdf]
- [5] S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, and M. Hashimoto, "Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2016. [pdf]
- [6] S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, "Neutron-Induced SEU and MCU Rate Characterization and Analysis of SOTB and Bulk SRAMs at 0.3V Operation," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.
- [7] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.