Search: 簡易 | 詳細 || Language: 英語 | 日本語 || ログイン |

512 件の該当がありました. : このページのURL : HTML


論文誌
[1] T. Nakayama and M. Hashimoto, "Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, 採録済.
[2] W. Liao and M. Hashimoto, "Analyzing Impacts of Sram, Ff and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate," IEICE Trans. on Electronics, 採録済.
[3] S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto, and Y. Watanabe, "Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-Nm Bulk Srams," IEEE Transactions on Nuclear Science, 採録済.
[4] Y. Masuda and M. Hashimoto, "Mttf-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, 採録済.
[5] M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, and Y. Watanabe, "Characterizing Sram and Ff Soft Error Rates with Measurement and Simulation (Invited)," Integration, the VLSI Journal, 採録済.
[6] W. Liao, M. Hashimoto, S. Manabe, S. Abe, and Y. Watanabe, "Similarity Analysis on Neutron- and Negative Moun-Induced Mcus in 65-Nm Bulk Sram," IEEE Transactions on Nuclear Science, 採録済.
[7] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, and S. Abe, "Estimation of Muon-Induced Seu Rates for 65-Nm Bulk and Utbb-Soi Srams," IEEE Transactions on Nuclear Science, 採録済.
[8] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, and T. Sakamoto, "Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture," IEEE Embedded Systems Letters, volume 10, number 4, 119 -- 122, December 2018. [desc]
[9] H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, and M. Hashimoto, "Via-Switch Fpga: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars," IEEE Transactions on VLSI Systems, volume 26, number 12, pages 2723--2736, December 2018. [pdf]
[10] Y. Masuda, T. Onoye, and M. Hashimoto, "Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving," IEEE Transactions on VLSI Systems, volume 26, number 11, pages 2217--2229, November 2018. [pdf]
[11] K. Mitsunari, J. Yu, T. Onoye, and M. Hashimoto, "Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E101-A, number 9, pages 1298--1307, September 2018. [pdf]
[12] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, S. Abe, K. Hamada, M. Tampo, and Y. Miyake, "Negative and Positive Muon-Induced Single Event Upsets in 65-Nm Utbb Soi Srams," IEEE Transactions on Nuclear Science, volume 65, number 8, pages 1742--1749, August 2018. [pdf]
[13] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, "Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65nm Bulk Srams," IEEE Transactions on Nuclear Science, volume 65, number 8, pages 1734--1741, August 2018. [pdf]
[14] B. Li, M. Hashimoto, and U. Schlichtmann , "From Process Variations to Reliability: a Survey of Timing of Digital Circuits in the Nanometer Era (Invited)," IPSJ Transactions on System LSI Design Methodology, volume 11, pages 2--15, February 2018.
[15] R. Doi, M. Hashimoto, and T. Onoye, "An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication," International Journal of Embedded Systems, volume 10, number 1, pages 22-31, January 2018.
[16] Y. Masuda, T. Onoye, and M. Hashimoto, "Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E100-A, number 7, pages 1452--1463, July 2017.
[17] C.-C. Hsu, M. Hashimoto, and P.-H. Lin, "Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits," Integration, the VLSI Journal, volume 58, pages 236--244, June 2017. [233.pdf]
[18] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E98-A, number 12, pages 2607--2613, December 2015.
[19] D. Fukuda, K. Watanabe, Y. Kanazawa, and M. Hashimoto, "Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-The-Fly Etching Process Modification," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E98-A, number 7, pages 1467--1474, July 2015. [221.pdf]
[20] T. Shinada, M. Hashimoto, and T. Onoye, "Proximity Distance Estimation Based on Electric Field Communication between 1mm³ Sensor Nodes," Analog Integrated Circuits and Signal Processing, May 2015. [220.pdf]
[21] S. Hirokawa, R. Harada, M. Hashimoto, and T. Onoye, "Characterizing Alpha- and Neutron-Induced Seu and Mcu on Sotb and Bulk 0.4-V Srams," IEEE Transactions on Nuclear Science, volume 62, number 2, pages 420--427, April 2015. [219.pdf]
[22] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Exploring Well-Configurations for Minimizing Single Event Latchup," IEEE Transactions on Nuclear Science, volume 61, number 6, pages 3282--3289, December 2014. [211.pdf]
[23] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2518--2529, December 2014. [210.pdf]
[24] T. Amaki, M. Hashimoto, and T. Onoye, "A Process and Temperature Tolerant Oscillator-Based True Random Number Generator," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2393--2399, December 2014. [208.pdf]
[25] D. Fukuda, K. Watanabe, N. Idani, Y. Kanazawa, and M. Hashimoto, "Edge-Over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2373--2382, December 2014. [209.pdf]
[26] H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1468--1482, July 2014. [201.pdf]
[27] H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Nbti Mitigation Method by Inputting Random Scan-In Vectors in Standby Time," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1483--1491, July 2014. [202.pdf]
[28] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Set Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1461--1467, July 2014. [200.pdf]
[29] H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10t Subthreshold Sram," IEEE Transactions on Device and Materials Reliability, volume 14, number 1, 463 -- 470, March 2014. [185.pdf]
[30] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Bit-Upset with Well-Slits in 28 Nm Multi-Bit-Latch," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4362--4367, December 2013. [197.pdf]
[31] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in Sram at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4232--4237, December 2013. [198.pdf]
[32] D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture," IEEE Transactions on VLSI Systems, volume 21, number 12, 2165 -- 2178, December 2013. [177.pdf]
[33] K. Shinkai, M. Hashimoto, and T. Onoye, "A Gate-Delay Model Focusing on Current Fluctuation Over Wide Range of Process-Voltage-Temperature Variations," Integration, the VLSI Journal, volume 46, number 4, pages 345--358, September 2013. [179.pdf]
[34] T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices," IEICE Trans. on Information and Systems , volume E96-D, number 8, pages 1624--1631, August 2013. [191.pdf]
[35] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling," IEEE Transactions on Information Forensics and Security, volume 8, number 8, pages 1331--1342, August 2013. [190.pdf]
[36] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Impact of Nbti-Induced Pulse-Width Modulation on Set Pulse-Width Measurement," IEEE Transactions on Nuclear Science, volume 60, number 4, pages 2630--2634, August 2013. [180.pdf]
[37] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices," IEICE Electronics Express (ELEX), volume 10, number 5, April 2013. [184.pdf]
[38] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Supply Noise Suppression by Triple-Well Structure," IEEE Transactions on VLSI Systems, volume 21, number 4, pages 781--785, April 2013. [169.pdf]
[39] I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, "A 0.8-V 110-Na Cmos Current Reference Circuit Using Subthreshold Operation," IEICE Electronics Express (ELEX), volume 10, number 4, March 2013. [182.pdf]
[40] T. Amaki, M. Hashimoto, and T. Onoye, "Jitter Amplifier for Oscillator-Based True Random Number Generator," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E96-A, number 3, pages 684--696, March 2013. [181.pdf]
[41] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E96-A, number 2, pages 459--468, February 2013. [178.pdf]
[42] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," IEEE Transactions on Nuclear Science, volume 59, number 6, pages 2791--2795, December 2012. [175.pdf]
[43] T. Enami, T. Sato, and M. Hashimoto, "Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2261--2271, December 2012. [171.pdf]
[44] Y. Takai, M. Hashimoto, and T. Onoye, "Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2220--2225, December 2012. [172.pdf]
[45] S. Kimura, M. Hashimoto, and T. Onoye, "A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2292--2300, December 2012. [173.pdf]
[46] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 20, number 2, pages 333--343, February 2012. [155.pdf]
[47] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Stress Probability Computation for Estimating Nbti-Induced Delay Degradation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 12, pages 2545--2553, December 2011. [166.pdf]
[48] K. Shinkai, M. Hashimoto, and T. Onoye, "Extracting Device-Parameter Variations with Ro-Based Sensors," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 12, pages 2537--2544, December 2011. [165.pdf]
[49] T. Okumura and M. Hashimoto, "Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 10, pages 1948--1953, October 2011. [164.pdf]
[50] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," IEEE Transactions on Nuclear Science, volume 58, number 4, pages 2097--2102, August 2011. [159.pdf]
[51] H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, "An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion," IEEE Transactions on Circuits and Systems II, volume 58, number 5, pages 299--303, May 2011. [158.pdf]
[52] S. Ninomiya and M. Hashimoto, "Accuracy Enhancement of Grid-Based Ssta by Coefficient Interpolation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2441--2446, December 2010. [150.pdf]
[53] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Measurement Circuits for Acquiring Set Pulse Width Distribution with Sub-Fo1-Inverter-Delay Resolution," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2417--2423, December 2010. [149.pdf]
[54] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, "Gate Delay Estimation in Sta under Dynamic Power Supply Noise," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2447--2455, December 2010. [151.pdf]
[55] T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, 2399--2408 , December 2010. [148.pdf]
[56] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 18, number 7, pages 1118--1129, July 2010. [130.pdf]
[57] 密山幸男, 高橋一真, 今井林太郎, 橋本昌宜, 尾上孝雄, 白川功, "メディア処理向け再構成可能アーキテクチャでの動画像復号処理の実現," 電子情報通信学会論文誌A, volume J93-A, number 6, pages 397--413, 2010年6月. [144.pdf]
[58] T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, and M. Hashimoto, "Impact of Self-Heating in Wire Interconnection on Timing," IEICE Trans. on Electronics, volume E93-C, number 3, pages 388--392, March 2010. [136.pdf]
[59] K. Shinkai, M. Hashimoto, and T. Onoye, "Prediction of Self-Heating in Short Intra-Block Wires," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 3, pages 583--594, March 2010. [135.pdf]
[60] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for Cmos Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , volume 29, number 2, pages 250--260, February 2010. [134.pdf]
[61] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3094--3102, December 2009. [128.pdf]
[62] T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto, "An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3016--3023, December 2009. [129.pdf]
[63] A. Kurokawa, T. Sato, T. Kanamoto, and M. Hashimoto, "Interconnect Modeling: a Physical Design Perspective (Invited)," IEEE Transactions on Electron Devices, volume 56, number 9, pages 1840--1851, September 2009. [126.pdf]
[64] Y. Ogasahara, M. Hashimoto, and T. Onoye, "All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform," IEEE Journal of Solid-State Circuits, volume 44, number 6, pages 1745--1755, June 2009. [124.pdf]
[65] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , volume 28, number 4, 541 - 553, April 2009. [118.pdf]
[66] T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, "Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 92-A, number 4, pages 990--997, April 2009. [119.pdf]
[67] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," IEICE Trans. on Electronics, volume E92-C, number 2, pages 281--285, February 2009. [117.pdf]
[68] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3461-3464, December 2008. [111.pdf]
[69] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3481-3487, December 2008. [112.pdf]
[70] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, "Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3474-3480, December 2008. [113.pdf]
[71] Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa, "Area-Efficient Reconfigurable Architecture for Media Processing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3651-3662, December 2008. [114.pdf]
[72] 渡辺慎吾, 橋本昌宜, 佐藤寿倫, "タイミング歩留まり改善を目的とする演算器カスケーディング," 情報処理学会論文誌コンピューティングシステム, volume 1, number 2, pages 12--21, 2008年8月. [108.pdf]
[73] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," IEICE Trans. on Information and Systems , volume E91-D, number 3, pages 655--660, March 2008. [101.pdf]
[74] 高橋真吾, 築山修治, 橋本昌宜, 白川功, "液晶ディスプレイ用サンプリング回路におけるサンプリングパルスとトランジスタサイズの最適設計手法," 電子情報通信学会論文誌A, volume J91-A, number 3, pages 373-382, 2008年3月. [100.pdf]
[75] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects," IEEE Journal of Solid-State Circuits, volume 43, number 3, pages 718--728, March 2008. [99.pdf]
[76] M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, and I. Shirakawa, "Transistor Sizing of Lcd Driver Circuit for Technology Migration," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 12, pages 2712--2717, December 2007. [96.pdf]
[77] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 12, pages 2661-2668, December 2007. [95.pdf]
[78] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Trans. on CAS-II, volume 54, number 10, pages 868--872, October 2007. [94.pdf]
[79] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling," IEICE Trans. on Electronics, volume E90-C, number 6, pages 1267-1273, June 2007. [88.pdf]
[80] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 4, pages 724--731, April 2007. [80.pdf]
[81] H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, and M. Hashimoto, "Proposal of Metrics for Ssta Accuracy Evaluation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 4, pages 808--814, April 2007. [81.pdf]
[82] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3538-3545, December 2006. [1.pdf]
[83] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect Rl Extraction Based on Transfer Characteristics of Transmission-Line," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3585-3593, December 2006. [2.pdf]
[84] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006. [3.pdf]
[85] T. Sato, J. Ichimiya, N. Ono, and M. Hashimoto, "On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3491-3499, December 2006. [4.pdf]
[86] T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, and M Hashimoto, "Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3666-3670, December 2006. [5.pdf]
[87] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "グラウンド平面・シールド配線によるシステム・オン・パネルの配線間容量の低減と容量見積もりの容易化," 情報処理学会論文誌, volume 47, number 6, pages 1665-1673, 2006年6月.
[88] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation in H-Tree Structure," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pp.3375-3381, December 2005. [6.pdf]
[89] A. Muramatsu, M. Hashimoto, and H. Onodera, "Effects of On-Chip Inductance on Power Distribution Grid," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3564-3572, December 2005. [7.pdf]
[90] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment for Minimizing Supply Voltage Drop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A,, number 12, pages 3429-3436, December 2005. [8.pdf]
[91] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3382-3389, December 2005. [9.pdf]
[92] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, , Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]
[93] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "システム液晶のための配線容量抽出手法," 情報処理学会論文誌, volume 46, number 6, pages 1395-1403, 2005年6月.
[94] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 4, pages 885-891, April 2005. [11.pdf]
[95] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll," IEICE Trans. on Electronics, volume E88-C, number 3, pages 437-444, March 2005. [89.pdf]
[96] M. Hashimoto and H. Onodera, "Crosstalk Noise Optimization by Post-Layout Transistor Sizing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E87-A, number 12, pages 3251-3257, December 2004. [12.pdf]
[97] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , volume 23, number 4, pages 498-508, April 2004. [20.pdf]
[98] M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk Noise Estimation for Generic Rc Trees," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 2965-2973, December 2003. [13.pdf]
[99] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(F)L(F)C Extraction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 2942-2951, December 2003. [14.pdf]
[100] M. Hashimoto, Y. Hayashi, and H. Onodera, "Experimental Study on Cell-Base High-Performance Datapath Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 3204-3207, December 2003. [15.pdf]
[101] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜, "遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会論文誌, volume 44, number 5, pages 1301-1310, 2003年5月. [21.pdf]
[102] M. Hashimoto and H. Onodera, "Increase in Delay Uncertainty by Performance Optimization," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 12, pages 2799-2802, December 2002. [16.pdf]
[103] 土谷亮, 橋本昌宜, 小野寺秀俊, "VLSI 配線の伝送線路特性を考慮した駆動力決定手法," 情報処理学会論文誌, volume 43, number 5, pages 1338--1347, 2002年5月. [63.pdf]
[104] M. Hashimoto and H. Onodera, "Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E84-A, number 11, pages 2769-2777, November 2001. [17.pdf]
[105] M. Hashimoto and H. Onodera, "A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E83-A, number 12, pages 2558-2568, December 2000. [18.pdf]
[106] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法," 情報処理学会論文誌, volume 40, number 4, pages 1707-1716, 1999年4月.
[107] M. Hashimoto, H. Onodera, and K. Tamaru, "A Power and Delay Optimization Method Using Input Reordering in Cell-Based Cmos Circuits," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E82-A, number 1, pages 159-166, January 1999. [19.pdf]
国際会議
[1] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, S. Takeshita, and Y. Miyake, "Negative and Positive Muon-Induced Seu Cross Sections in 28-Nm and 65-Nm Planar Bulk Cmos Srams," Proceedings of International Reliability Physics Symposium (IRPS), 採録済.
[2] J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, and Y. Momiyama, "Activation-Aware Slack Assignment (Asa) for Mode-Wise Power Saving in High-End Isp," Design Automation Conference, Designer/IP Track, 採録済.
[3] P. Chen, R. Shirai, and M. Hashimoto, "Coverage-Scalable Instant Tabletop Positioning System with Self-Localizable Anchor Nodes," Proceedings of International Conference on Intelligent User Interfaces (IUI), March 2019.
[4] R. Doi, J. Yu, and M. Hashimoto, "Sneak Path Free Reconfiguration of Via-Switch Crossbars Based Fpga," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2018. [pdf]
[5] Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, and M. Hashimoto, "Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2018. [pdf]
[6] K. Mitsunari, J. Yu, and M. Hashimoto, "Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 55-58, November 2018. [pdf]
[7] M. Hashimoto, W. Liao, S. Manabe, and Y. Watanabe, "Characterizing Soft Error Rates of 65-Nm Sotb and Bulk Srams with Muon and Neutron Beams (Invited)," Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2018. [pdf]
[8] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, and S. Abe, "Estimation of Muon-Induced Seu Rates for 65-Nm Bulk and Utbb-Soi Srams," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.
[9] W. Liao, M. Hashimoto, S. Manabe, S. Abe, and Y. Watanabe, "Similarity Analysis on Neutron- and Negative Moun-Induced Mcus in 65-Nm Bulk Sram," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.
[10] S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto, and Y. Watanabe, "Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-Nm Bulk Srams," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.
[11] K. Itoh, J. Yu, and M. Hashimoto, "Adapting Soft Cascsde to Mac Operations of Convolutional Neural Networks," Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC), August 2018.
[12] R. Doi and M. Hashimoto, "Sat Encoding-Based Verification of Sneak Path Problem in Via-Switch Fpga," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018. [desc]
[13] M. Hashimoto, Y. Nakazawa, R. Doi, and J. Yu, "Interconnect Delay Analysis for Rram Crossbar Based Fpga (Invited)," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018. [desc]
[14] L. Zhang, B. Li, and M. Hashimoto. U. Schlichtmann, "Virtualsync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units," Proceedings of Design Automation Conference (DAC), June 2018. [desc]
[15] R. Shirai, T. Hirose, and M. Hashimoto, "A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes," Proceedings of International NEWCAS Conference, June 2018.
[16] J. Chen, T. Kanamoto, H. Kando, and M. Hashimoto, "An On-Chip Load Model for Off-Chip Pdn Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency," Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), May 2018.
[17] T. Nakayama and M. Hashimoto, "Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature," Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2018. [pdf]
[18] K.-W. Lin, M. Hashimoto, and Y.-L. Li, "Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles Considering Traffic Uncertainties," Proceedings of International Symposium on Quality Electronic Design (ISQED), March 2018.
[19] M. Hashimoto and Y. Masuda, "Mttf-Aware Design Methodology for Adaptive Voltage Scaling (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2018.
[20] Y. Masuda and M. Hashimoto, "Mttf-Aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018.
[21] R. Shirai, T. Hirose, and M. Hashimoto, "Dedicated Antenna Less Power Efficient Ook Transmitter for Mm-Cubic Iot Nodes," Proceedings of European Microwave Conference (EuMC), pages 101--104, October 2017. [desc]
[22] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, "Measurement and Mechanism Investigation of Negative and Positive Muon Induced Upsets in 65nm Bulk Srams," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2017.
[23] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, "Momentum and Supply Voltage Dependencies of Seus Induced by Low-Energy Negative and Positive Muons in 65-Nm Utbb-Soi Srams," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2017.
[24] M. Hashimoto, R. Shirai, Y. Itoh, and T. Hirose, "Toward Real-Time 3d Modeling System with Cubic-Millimeters Wireless Sensor Nodes (Invited)," Proceedings of IEEE International Conference on ASIC, pages 1087--1091, October 2017.
[25] M. Hashimoto, W. Liao, and S. Hirokawa, "Soft Error Rate Estimation with Tcad and Machine Learning (Invited)," Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2017. [pdf]
[26] K.-W. Lin, Y.-L. Li, and M. Hashimoto, "Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles," Proceedings of IEEE Intelligent Vehicles Symposium (IV), pages 1465--1470, June 2017.
[27] W. Liao, S. Hirokawa, R. Harada, and M. Hashimoto, "Contributions of Sram, Ff and Combinational Circuit to Chip-Level Neutron-Induced Soft Error Rate -- Bulk Vs. Fd-Soi at 0.5 and 1.0v --," Proceedings of International NEWCAS Conference, pages 33-37, June 2017. [desc]
[28] R. Shirai, J. Kono, T. Hirose, and M. Hashimoto, "Near-Field Dual-Use Antenna for Magnetic-Field Based Communication and Electrical-Field Based Distance Sensing in Mm^3-Class Sensor Node," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pages 124--127, May 2017.
[29] S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, "Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices," Proceedings of IEEE Wireless Power Transfer Conference (WPTC), May 2017.
[30] K. Hirosue, S. Ukawa, Y. Itoh, T. Onoye, and M. Hashimoto, "Gpgpu-Based Highly Parallelized 3d Node Localization for Real-Time 3d Model Reproduction," Proceedings of International Conference on Intelligent User Interfaces (IUI), pages 173--178, March 2017.
[31] N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "50x20 Crossbar Switch Block (Csb) with Two-Varistors (A-Si/Sin/A-Si) Selected Complementary Atom Switch for a Highly-Dense Reconfigurable Logic," Technical Digest of IEEE International Electron Devices Meeting (IEDM), December 2016. [231.PDF]
[32] Y. Masuda, M. Hashimoto, and T. Onoye, "Critical Path Isolation for Time-To-Failure Extension and Lower Voltage Operation," Proceedings of International Conference on Computer-Aided Design (ICCAD), November 2016. [230.pdf]
[33] Y. Akihara, T. Hirose, S. Masuda, N. Kuroki, M. Numa, and M. Hashimoto, "Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems," Proceedings of International Symposium on Antennas and Propagation (ISAP), October 2016. [232.pdf]
[34] S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, "Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes," Proceedings of International Symposium on Antennas and Propagation (ISAP), October 2016.
[35] H.-Y. Su, B.-S. Wang, S.-Y. Hsieh, Y.-L. Li, I-H. Wu, C.-C. Wu, W.-C. Shih, H. Onodera, and M. Hashimoto, "Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2016.
[36] S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, and M. Hashimoto, "Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2016. [pdf]
[37] H. Hihara, A. Iwasaki, N. Tamagawa, M. Kuribayashi, M. Hashimoto, Y. Mitsuyama, H. Ochi, H. Onodera, H. Kanbara, K. Wakabayashi, and T. Sugibayashi, "Novel Processor Architecture for Onboard Infrared Sensors (Invited)," Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV, volume 9973, August 2016.
[38] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2016.
[39] Y. Masuda, M. Hashimoto, and T. Onoye, "Hardware-Simulation Correlation of Timing Error Detection Performance of Software-Based Error Detection Mechanisms," Proceedings of International On-Line Testing Symposium (IOLTS), pages 84--89, July 2016. [228.pdf]
[40] C.-C. Hsu, M. P.-H. Lin, and M. Hashimoto, "Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits," Proceedings of System Level Interconnect Prediction (SLIP) Workshop, June 2016. [229.pdf]
[41] Y. Masuda, M. Hashimoto, and T. Onoye, "Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.
[42] R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.
[43] U. Schlichtmann, M. Hashimoto, I. H.-R. Jiang, and B. Li, "Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits (Invited)," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 705--711, January 2016. [227.pdf]
[44] N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "A Novel Two-Varistors (A-Si/Sin/A-Si) Selected Complementary Atom Switch (2v-1cas) for Nonvolatile Crossbar Switch with Multiple Fan-Outs," Technical Digest of IEEE International Electron Devices Meeting (IEDM), pages 32--35, December 2015. [225.PDF]
[45] Y. Masuda, M. Hashimoto, and T. Onoye, "Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise," Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 315-322, November 2015. [224.pdf]
[46] R. Doi, M. Hashimoto, and T. Onoye, "An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication," Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), November 2015.
[47] S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, "Stochastic Timing Error Rate Estimation under Process and Temporal Variations," Proceedings of International Test Conference (ITC), October 2015. [223.pdf]
[48] Y. Akihara, T. Hirose, Y. Tanaka, N. Kuroki, M. Numa, and M. Hashimoto, "A Wireless Power Transfer System for Small-Sized Sensor Applications," Proceedings of International Conference on Solid State Devices and Materials (SSDM), pages 154--155, September 2015.
[49] S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, "Neutron-Induced Seu and Mcu Rate Characterization and Analysis of Sotb and Bulk Srams at 0.3v Operation," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.
[50] M. Ueno, M. Hashimoto, and T. Onoye, "Real-Time On-Chip Supply Voltage Sensor and Its Application to Trace-Based Timing Error Localization," Proceedings of International On-Line Testing Symposium (IOLTS), pages 188--193, July 2015. [222.pdf]
[51] M. Hashimoto, "Run-Time Performance Adaptation: Opportunities and Challenges (Invited)," Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), June 2015. [226.pdf]
[52] T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, "Impact of Package on Neutron Induced Single Event Upset in 20 Nm Sram," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015. [215.pdf]
[53] T. Uemura and M. Hashimoto, "Investigation of Single Event Upset and Total Ionizing Dose in Feram for Medical Electronic Tag," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015. [216.pdf]
[54] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 Nm Bulk Cmos," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]
[55] S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, and T. Onoye, "3d Node Localization from Node-To-Node Distance Information Using Cross-Entropy Method," Proceedings of Virtual Reality Conference (VR), March 2015. [218.pdf]
[56] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 731--736, January 2015. [214.pdf]
[57] M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 14--15, January 2015. [213.pdf]
[58] T. Amaki, M. Hashimoto, and T. Onoye, "An Oscillator-Based True Random Number Generator with Process and Temperature Tolerance," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 4--5, January 2015. [212.pdf]
[59] M. Hashimoto, "Stochastic Verification of Run-Time Performance Adaptation with Field Delay Testing (Invited)," Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS), pages 751--754, November 2014. [207.pdf]
[60] M. Hashimoto, "Opportunities and Verification Challenges of Run-Time Performance Adaptation (Invited)," Proceedings of Asian Test Symposium (ATS), pages 248--253, November 2014. [206.pdf]
[61] M. Hashimoto, "Toward Robust Subthreshold Circuit Design: Variability and Soft Error Perspective (Invited)," Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2014. [205.pdf]
[62] A. Iokibe, M. Hashimoto, and T. Onoye, "Feasibility Evaluation on an Instant Invader Detection System with Ultrasonic Sensors Scattered on the Ground," Proceedings of International Conference on Sensing Technology (ICST), pages 188--193, September 2014. [204.pdf]
[63] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Optimizing Well-Configuration for Minimizing Single Event Latchup," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[64] R. Harada, S. Hirokawa, and M. Hashimoto, "Measurement of Alpha- and Neutron-Induced Seu and Mcu on Sotb and Bulk 0.4 V Srams," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[65] T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, "Preventing Single Event Latchup with Deep P-Well on P-Substrate," Proceedings of International Reliability Physics Symposium (IRPS), June 2014. [203.pdf]
[66] M. Ueno, M. Hashimoto, and T. Onoye, "Trace-Based Fault Localization with Supply Voltage Sensor," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 77--81, March 2014.
[67] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, and T. Onoye, "Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design," Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2013. [199.pdf]
[68] S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, and T. Onoye, "Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing," Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 107--114, November 2013. [193.PDF]
[69] J. Kono, M. Hashimoto, and T. Onoye, "Feasibility Evaluation of Near-Field Communication in Clay with 1-Mm^3 Antenna," Proceedings of Asia-Pacific Microwave Conference (APMC), pages 1121--1123, November 2013. [194.pdf]
[70] T. Amaki, M. Hashimoto, and T. Onoye, "A Process and Temperature Tolerant Oscillator-Based True Random Number Generator with Dynamic 0/1 Bias Correction," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 133--136, November 2013. [195.pdf]
[71] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 313--316, November 2013. [196.pdf]
[72] R. Harada, M. Hashimoto, and T. Onoye, "Nbti Characterization Using Pulse-Width Modulation," IEEE/ACM Workshop on Variability Modeling and Characterization, November 2013.
[73] M. Hashimoto, "Soft Error Immunity of Subthreshold Sram (Invited)," Proceedings of IEEE International Conference on ASIC, pages 91--94, October 2013. [192.pdf]
[74] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Scaling Trend of Sram and Ff of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk Cmos Technology," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[75] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in Sram at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[76] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[77] T. Shinada, M. Hashimoto, and T. Onoye, "Proximity Distance Estimation Based on Capacitive Coupling between 1mm^3 Sensor Nodes," Proceedings of International NEWCAS Conference, June 2013. [188.pdf]
[78] M. Ueno, M. Hashimoto, and T. Onoye, "Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures," Proceedings of Reconfigurable Architectures Workshop (RAW), pages 301--305, May 2013. [187.pdf]
[79] Y. Higuchi, K. Shinkai, M. Hashimoto, R. Rao, and S. Nassif, "Extracting Device-Parameter Variations Using a Single Sensitivity-Configurable Ring Oscillator," Proceedings of IEEE European Test Symposium (ETS), pages 106--111, May 2013. [186.pdf]
[80] M. Hashimoto, "Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability (Invited)," China Semiconductor Technology International Conference (CSTIC), pages 1079--1084, March 2013. [183.pdf]
[81] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices," Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012. [174.pdf]
[82] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Converter Based on Minimax Sampling," Proceedings of International SoC Design Conference (ISOCC), 120 -- 123 , November 2012. [176.pdf]
[83] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Impact of Nbti-­Induced Pulse-Width Modulation on Set Pulse-Width Measurement," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2012.
[84] T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012. [170.pdf]
[85] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2012.
[86] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Set Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects," Proceedings of International Reliability Physics Symposium (IRPS), April 2012. [168.PDF]
[87] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 283--289, February 2012. [167.pdf]
[88] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , pages 189--194, September 2011. [162.pdf]
[89] Y. Takai, M. Hashimoto, and T. Onoye, "Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2011. [163.pdf]
[90] T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Nbti Mitigation by Giving Random Scan-In Vectors During Standby Mode," Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pages 152--161, September 2011.
[91] M. Hashimoto and H. Fuketa, " Adaptive Performance Compensation with On-Chip Variation Monitoring (Invited)," Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011. [160.pdf]
[92] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling," Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011. [161.pdf]
[93] T. Amaki, M. Hashimoto, and T. Onoye, "An Oscillator-Based True Random Number Generator with Jitter Amplifier," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pages 725--728, May 2011. [157.pdf]
[94] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing," Proceedings of International Reliability Physics Symposium (IRPS), pages 253--257, April 2011. [156.PDF]
[95] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 46--51, April 2011.
[96] K. Shinkai, M. Hashimoto, and T. Onoye, "Extracting Device-Parameter Variations with Ro-Based Sensors," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 13--18, March 2011.
[97] D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability," IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.
[98] K. Shinkai and M. Hashimoto, "Device-Parameter Estimation with On-Chip Variation Sensors Considering Random Variability," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 683--688, January 2011. [152.pdf]
[99] T. Amaki, M. Hashimoto, and T. Onoye, "Jitter Amplifier for Oscillator-Based True Random Number Generator," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 81--82, January 2011. [153.pdf]
[100] M. Hashimoto, "Run-Time Adaptive Performance Compensation Using On-Chip Sensors (Invited)," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 285--290, January 2011. [154.pdf]
[101] Y. Takai, M. Hashimoto, and T. Onoye, "Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation," Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pages 213--216, October 2010. [146.pdf]
[102] T. Okumura and M. Hashimoto, "Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2010. [147.pdf]
[103] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling," Proceedings of International Workshop on Information Security Applications (WISA), pages 107-121, August 2010.
[104] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," Proceedings of International Reliability Physics Symposium (IRPS), pages 213--217, May 2010. [140.PDF]
[105] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," ACM Great Lake Symposium on VLSI (GLSVLSI), pages 197--202, May 2010. [143.pdf]
[106] Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to Sso," Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 19--20, May 2010. [139.pdf]
[107] D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, "A 16-Bit Risc Processor with 4.18pj/Cycle at 0.5v Operation," Proceedings of IEEE COOL Chips, page 190, April 2010. [145.pdf]
[108] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 646--651, March 2010. [137.pdf]
[109] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Measurement Circuits for Acquiring Set Pulse Width Distribution with Sub-Fo1-Inverter-Delay Resolution," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 839--844, March 2010. [138.pdf]
[110] T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 41--46, March 2010.
[111] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 89--94, March 2010.
[112] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, "Gate Delay Estimation in Sta under Dynamic Power Supply Noise," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 775 -- 780, January 2010. [132.pdf]
[113] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 361 -- 362, January 2010. [131.pdf]
[114] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Soft Error Resilient Vlsi Architecture for Signal Processing," Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 183--186, December 2009. [142.pdf]
[115] S. Ninomiya and M. Hashimoto, " Enhancement of Grid-Based Spatially-Correlated Variability Modeling for Improving Ssta Accuracy," Proceedings of IEEE International SOC Conference (SOCC), pages 337--340, September 2009. [141.pdf]
[116] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 215--218, September 2009. [127.pdf]
[117] K. Hamamoto, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 51--56, August 2009. [125.pdf]
[118] D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 186--192, August 2009. [133.pdf]
[119] S. Watanabe, M. Hashimoto, and T. Sato, "A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 401--407, March 2009. [122.pdf]
[120] Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 236--241, March 2009.
[121] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability," Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.
[122] K. Shinkai and M. Hashimoto, "A Gate Delay Model Over Wide-Range of Process and Environmental Variability," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 79--84, February 2009.
[123] L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, "High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 385--390, January 2009. [115.pdf]
[124] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 266-271, January 2009. [116.pdf]
[125] T. Enami, M. Hashimoto, and T. Sato, "Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 420--425, November 2008. [110.pdf]
[126] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 397--400, November 2008. [109.pdf]
[127] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits," Proceedings of Workshop on Test Structure Design for Variability Characterization, November 2008.
[128] Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, and C.-K. Cheng, "On-Chip High Performance Signaling Using Passive Compensation," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 182-187, October 2008. [123.pdf]
[129] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 3--8, August 2008. [106.pdf]
[130] S. Watanabe, M. Hashimoto, and T. Sato, "Cascading Dependent Operations for Mitigating Timing Variability," Proceedings. of Workshop on Quality-Aware Design (W-QUAD), June 2008. [105.pdf]
[131] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays," In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2008.
[132] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Experimental Study on Body-Biasing Layout Style -- Negligible Area Overhead Enables Sufficient Speed Controllability --," Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI), pages 387--390, May 2008. [104.pdf]
[133] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," Proceedings of ACM International Symposium on Physical Design (ISPD), pages 160-167, April 2008. [107.pdf]
[134] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 520--525, March 2008. [102.PDF]
[135] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site Soc Power Integrity Verification," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 107--108, January 2008. [97.pdf]
[136] L. Zhang, J. Liu, H. Zhu, C-K Cheng, and M. Hashimoto, "High Performance Current-Mode Differential Logic," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 720--725, January 2008. [98.pdf]
[137] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 233-237, October 2007.
[138] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," Proceedings of 37th European Solid-State Device Research Conference (ESSDERC), pages 115--118, September 2007. [92.pdf]
[139] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 783--786, September 2007. [90.pdf]
[140] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and Chung-Kuan Cheng, "Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 869--872, September 2007. [91.pdf]
[141] K. Shinkai, M. Hashimoto, and T. Onoye, "Future Prediction of Self-Heating in Short Intra-Block Wires," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 660-665, March 2007. [82.PDF]
[142] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 47-53, November 2006. [22.pdf]
[143] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects," In Proceedings of IEEE International Conference on Computer Design (ICCD), pages 70-75, October 2006. [23.pdf]
[144] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 721-724, September 2006. [24.pdf]
[145] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC),, pages 861-864, September 2006. [25.pdf]
[146] T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, and I. Shirakawa, "Transistor Sizing of Lcd Driver Circuit for Technology Migration," In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), volume 1, I25-I28, July 2006. [28.pdf]
[147] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227-230, May 2006. [65.pdf]
[148] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process Variations," In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 59-64, February 2006.
[149] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect Rl Extraction at a Single Representative Frequency," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 515-520, January 2006. [30.pdf]
[150] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction," In Proceedings of International Workshop on Compact Modeling (IWCM), pages 51-56, January 2006.
[151] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design for Liquid Crystal Displays," In Proceedings of IEEE International Region 10 Conference, number 1C-03.3, November 2005. [64.pdf]
[152] T. Kouno, M. Hashimoto, and H. Onodera, "Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 453-456, November 2005. [52.pdf]
[153] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip High-Throughput Global Signaling," In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 79-82, October 2005. [50.pdf]
[154] S. Uemura, T. Miyazaki, M. Hashimoto, and H. Onodera, "Estimation of Maximum Oscillation Frequency for Cmos Lcvcos," In Proceedings of IEEJ International Analog VLSI Workshop, October 2005.
[155] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Delay Variation Due to Inductive Coupling," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 305-308, September 2005. [26.pdf]
[156] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 613-616, September 2005. [27.pdf]
[157] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Scheme for Sampling Switch in Active Matrix Lcd," In Proceedings of European Conference on Circuit Theory and Design, number 3e-212, August 2005. [54.pdf]
[158] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer," In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 201-202, May 2005. [49.pdf]
[159] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, "Interconnect Capacitance Extraction for System Lcd Circuits," In Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pages 160-163, April 2005. [29.pdf]
[160] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics," In Proceedings of International Meeting for Future of Electron Devices, Kansai, pages 33-34, April 2005.
[161] A. Muramatsu, M. Hashimoto, and H. Onodera, "Effects of On-Chip Inductance on Power Distribution Grid," In Proceedings of International Symposium on Physical Design (ISPD), pages 63-69, April 2005. [46.pdf]
[162] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation in H-Tree Structure," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 402-407, March 2005. [51.PDF]
[163] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 723-728, January 2005. [31.pdf]
[164] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1098-1101, January 2005. [32.pdf]
[165] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Return Path Selection for Loop Rl Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1078-1081, January 2005. [33.pdf]
[166] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for Soc Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1074-1077, January 2005. [34.pdf]
[167] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um Cmos Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), D9-D10, January 2005. [35.pdf]
[168] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip Global Signaling," In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) , pages 87-100, November 2004.
[169] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 814-820, November 2004. [41.pdf]
[170] M. Hashimoto, A. Tsuchiya, and H. Onodera, "On-Chip Global Signaling by Wave Pipelining," In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 311-314, October 2004. [56.pdf]
[171] A. Muramatsu, M. Hashimoto, and H. Onodera, "Lsi Power Network Analysis with On-Chip Wire Inductance," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 55-60, October 2004.
[172] T. Sato, M. Hashimoto, and H. Onodera, "An Ir-Drop Minimization by Optimizing Number and Location of Power Supply Pads," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 66-72, October 2004.
[173] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 214-219, October 2004.
[174] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Prediction of Clock Generation Plls: a Ring Oscillator Based Pll and an Lc Oscillator Based Pll," In IEEJ International Analog VLSI Workshop, pages 45-50, October 2004.
[175] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 489-492, September 2004. [66.pdf]
[176] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Optimization of Cmos Current Mode Logic Dividers," In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits , pages 434-435, August 2004. [55.pdf]
[177] M. Hashimoto, K. Fujimori, and H. Onodera, "Automatic Generation of Standard Cell Library in Vdsm Technologies," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 36-41, March 2004. [53.PDF]
[178] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(F)L(F)C Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 691-696, January 2004. [37.pdf]
[179] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Comparison of Plls for Clock Generation Using Ring Oscillator Vco and Lc Oscillator in a Digital Cmos Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 545-546, January 2004. [36.pdf]
[180] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 169-175, November 2003. [42.pdf]
[181] M. Hashimoto, Y. Yamada, and H. Onodera, "Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis," In Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD), pages 18-23, April 2003. [45.pdf]
[182] Y. Yamada, M. Hashimoto, and H. Onodera, "Slew Calculation Against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 280-287, April 2003.
[183] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Frequency Determination for Interconnect Rlc Extraction," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 288-293, April 2003.
[184] T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, and M. Hashimoto, "Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 149-155, January 2003. [40.pdf]
[185] M. Hashimoto, K. Fujimori, and H. Onodera, "Standard Cell Libraries with Various Driving Strength Cells for 0.13, 0.18 and 0.35um Technologies," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 589-590, January 2003. [38.pdf]
[186] M. Hashimoto, D. Hiramatsu, A. Tsuchiya, and H. Onodera, "Interconnect Structures for High-Speed Long-Distance Signal Transmission," In Proceedings of IEEE International ASIC/SOC Conference, pages 426-430, September 2002. [57.pdf]
[187] M. Hashimoto, Y. Hayashi, and H. Onodera, "Experimental Study on Cell-Base High-Performance Datapath Design," In Proceedings of IEEE/ACM International Workshop on Logic & Synthesis (IWLS), pages 283-287, June 2002.
[188] M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk Noise Optimization by Post-Layout Transistor Sizing," In Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD), pages 126-130, April 2002. [43.pdf]
[189] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 377-381, October 2001.
[190] M. Takahashi, M. Hashimoto, and H. Onodera, "Crosstalk Noise Estimation for Generic Rc Trees," In Proceedings of International Conference on Computer Design (ICCD), pages 110-116, September 2001. [58.pdf]
[191] H. Onodera, M. Hashimoto, and T. Hashimoto, "Asic Design Methodology with On-Demand Library Generation," In Proceedings of Symposium on VLSI Circuits, pages 57-60, June 2001. [59.pdf]
[192] M. Hashimoto and H. Onodera, "Increase in Delay Uncertainty by Performance Optimization," In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), volume V, pages 379-382, May 2001. [60.pdf]
[193] M. Hashimoto and H. Onodera, "Post-Layout Transistor Sizing for Power Reduction in Cell-Based Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 359-365, January 2001. [39.pdf]
[194] M. Hashimoto and H. Onodera, "A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing," In Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 34-37, December 2000.
[195] T. Iwahashi, T. Shibayama, M. Hashimoto, K. Kobayashi, and H. Onodera, "Vector Quantization Processor for Mobile Video Communication," In Proceedings of IEEE International ASIC/SOC Conference, pages 75-79, September 2000. [61.pdf]
[196] M. Hashimoto and H. Onodera, "A Performance Optimization Method by Gate Sizing Using Statistical Static Timing Analysis," In Proceedings of ACM International Symposium on Physical Design (ISPD), pages 111-116, April 2000. [44.pdf]
[197] M. Hashimoto and H. Onodera, "A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis," In Proceedings of the Ninth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 115-121, April 2000.
[198] M. Hashimoto, H. Onodera, and K. Tamaru, "Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design," In Proceedings of the 36th IEEE/ACM Design Automation Conference (DAC), pages 446-451, June 1999. [47.pdf]
[199] M. Hashimoto, H. Onodera, and K. Tamaru, "A Power Optimization Method Considering Glitch Reduction by Gate Sizing," In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 221-226, August 1998. [48.pdf]
[200] M. Hashimoto, H. Onodera, and K. Tamaru, "Input Reordering for Power and Delay Optimization," In Proceedings of IEEE International ASIC Conference and Exhibit, pages 194-198, September 1997. [62.pdf]
国内会議(査読付き)
[1] 土井龍太郎, 劉載勲, 橋本昌宜, "ビアスイッチFPGA再構成時のスニークパス問題を回避するプログラミング順決定手法," 情報処理学会DAシンポジウム, 2018年8月.
[2] 増田豊, 長山準, 武野紘宜, 小川芳正, 籾山陽一, 橋本昌宜, "エラー予告FFとレプリカの電圧マージン制御性能の定量的比較," 情報処理学会DAシンポジウム, 2018年8月.
[3] 金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始, "FOWLPを用いたLSIにおける再配線層上キャパシタ及びオンチップ容量の最適化," 情報処理学会DAシンポジウム, 2018年8月.
[4] 佐藤雅紘, 増田豊, 橋本昌宜, "過電圧スケーリングを用いた不正確計算による消費電力削減の検討," 電子情報通信学会VLSI設計技術研究会, number VLD2017-123, 2018年3月.
[5] 中澤祐希, 土井龍太郎, 劉載勲, 橋本昌宜, "ビアスイッチFPGA向け配線遅延解析手法の検討," 電子情報通信学会 VLSI設計技術研究会, number VLD2017-120, 2018年3月.
[6] 葛西孝己, 神藤始, 陳俊, 橋本昌宜, 今井雅, 黒川敦, 金本俊幾, "容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築," 情報処理学会東北支部研究報告, 2018年2月.
[7] 白井僚, 河野仁, 廣瀬哲也, 橋本昌宜, "近傍界磁界通信・電界測距共用mm3級アンテナの実装と評価," 電子情報通信学会 回路とシステム研究会, 2017年12月.
[8] 白井僚, 廣瀬哲也, 橋本昌宜, "IoTノード向けアンテナ組込型小体積高効率トランスミッタの開発," 電子情報通信学会 集積回路研究会, 2017年12月.
[9] 橋本昌宜, "高エネルギー効率コンピューティングを実現するビアスイッチFPGA の開発 (Invited)," 電気関連学会関西連合大会, 2017年11月.
[10] 土井龍太郎, 橋本昌宜, "ビアスイッチFPGAにおけるスニークパス問題のSAT符号化を用いた検証," 情報処理学会DAシンポジウム, 2017年8月.
[11] 金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始, "容量配置最適化に向けた15nm世代LSI・パッケージ・ボード電源網解析モデルの構築," 情報処理学会DAシンポジウム, 2017年8月.
[12] 増田豊, 橋本昌宜, "エラー予告ベース適応的電圧制御のMTTF考慮設計手法," 情報処理学会DAシンポジウム, 2017年8月.
[13] 中山貴博, 橋本昌宜, "常温で論理テスト可能な超低温動作VLSIのタイミング設計法の検討," 情報処理学会DAシンポジウム, 2017年8月.
[14] 伴野直樹, 多田宗弘, 岡本浩一郎, 井口憲幸, 阪本利司, 波田博光, 越智裕之, 小野寺秀俊, 橋本昌宜, 杉林直彦, "低電力FPGAを実現するビアスイッチ技術を用いた大規模クロスバースイッチの実証 (Invited)," 電子情報通信学会シリコン材料・デバイス研究会, number SDM2016-144, 2017年2月.
[15] 増田豊, 尾上孝雄, 橋本昌宜, "低電圧・長寿命動作に向けたクリティカルパス・アイソレーション手法," 情報処理学会DAシンポジウム, 2016年9月.
[16] 佐藤雅紘, 増田豊, 飯塚翔一, 尾上孝雄, 橋本昌宜, "確率的回路寿命予測手法の計算安定性と確率取り扱いの妥当性に関する考察," 情報処理学会DAシンポジウム, 2016年9月.
[17] 橋本昌宜, "超低電圧SRAMのソフトエラー耐性 (Invited)," 電子情報通信学会 集積回路研究会, number ICD2016-22 , pages 53--58, 2016年8月.
[18] 秋原優樹, 廣瀬哲也, 田中勇気, 黒木修隆, 沼昌宏, 橋本昌宜, "小型センサデバイスに向けた無線給電システムの設計," 回路とシステムワークショップ, 258--263, 2015年8月.
[19] 増田豊, 橋本昌宜, 尾上孝雄, "電源ノイズ起因タイミング故障のデバッグにおけるC言語ベース故障検出手法の有効性評価," 情報処理学会DAシンポジウム, 2015年8月.
[20] 檜原弘樹, 岩崎晃, 橋本昌宜, 越智裕之, 密山幸男, 小野寺秀俊, 神原弘之, 若林一敏, 杉林直彦, 竹中崇, 波田博光, 多田宗弘, "センサの知能化に適したプロセッサアーキテクチャの考察," 電子情報通信学会ディペンダブルコンピューティング研究会, number DC2015-8, pages 43--48, 2015年4月.
[21] 佐藤雅紘, 飯塚翔一, 粟野皓光, 橋本昌宜, 尾上孝雄, "NBTIによる閾値電圧変化の確率的モデル化に関する一考察," 2015年電子情報通信学会総合大会講演論文集, 2015年3月.
[22] 河野仁, 橋本昌宜, 近藤利彦, 森村浩季, "超小型コイルを用いた近距離無線通信における周辺コイルの影響評価," 2015年電子情報通信学会総合大会講演論文集, 2015年3月.
[23] 益田涼平, 橋本昌宜, 尾上孝雄, "サーモパイル型赤外線センサを用いた人感センサの性能評価," 2015年電子情報通信学会総合大会講演論文集, 2015年3月.
[24] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," 電子情報通信学会 VLSI設計技術研究会, March 2015.
[25] 鵜川翔平,信田龍哉,橋本昌宜,伊藤雄一,尾上孝雄, "クロスエントロピー法を用いたノード間距離情報に基づく3次元ノード位置推定," 情報処理学会ヒューマンコンピュータインタラクション研究会, 2015年1月.
[26] 土井龍太郎, 橋本昌宜, 尾上孝雄, "時間的三重化によるソフトエラー耐性向上の解析的評価," 電子情報通信学会ディペンダブルコンピューティング研究会, 2014年11月.
[27] 飯塚翔一, 樋口裕磨, 橋本昌宜, 尾上孝雄, "感度可変リングオシレータを用いた省面積デバイスパラメータばらつき推定手法," 情報処理学会DAシンポジウム, pages 15--20, 2014年8月.
[28] 増田豊, 橋本昌宜, 尾上孝雄, "電源ノイズ起因電気的故障を対象としたソフトウェアベース高速エラー検出手法の性能評価," 情報処理学会DAシンポジウム, pages 203--208, 2014年8月.
[29] 飯塚翔一, 水野雅文, 黒田弾, 橋本昌宜, 尾上孝雄, "プロセッサの適応的速度制御における故障発生時間見積り高速化に関する研究," LSIとシステムのワークショップ, 2014年5月.
[30] 河野仁, 鵜川翔平, 信田龍哉, 塚元瑞穂, 田中勇気, 中島康祐, 伊藤雄一, 廣瀬哲也, 橋本昌宜, "リアルタイム3次元モデリングシステムiClayの実現に向けた1mm^3級センサノードの要素技術開発," LSIとシステムのワークショップ, 2014年5月.
[31] 鵜川翔平, 信田龍哉, 伊藤雄一, 橋本昌宜, 尾上孝雄, "ノード間距離情報に基づいた逐次的3次元ノード位置推定手法の検討," 電子情報通信学会 回路とシステム研究会, number CAS2012-119, pages 131--136, 2014年3月.
[32] 郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄, "動的部分再構成による故障回避に適した初期配置配線の検討," 情報処理学会SLDM研究会, 2014年3月.
[33] 橋本昌宜, "オンチップばらつきモニタリングによる適応的性能補償 (Invited)," 電子情報通信学会 集積回路研究会, number IEICE-ICD2013-100 , 2014年1月.
[34] 尾上孝雄, 橋本昌宜, 密山幸男, Dawood Alnajjar, 郡浦宏明, "VLSIの信頼性を向上させる再構成可能アーキテクチャ (Invited)," 電子情報通信学会リコンフィギャラブルシステム研究会, number IEICE-RECONF2013-51, 2013年11月.
[35] 作田賢志朗, 安部晋一郎, 渡辺幸信, 原田諒, 橋本昌宜, 更田裕司, 上村大樹, "宇宙線中性子起因マルチセルアップセットのスケーリング則調査," 応用物理学会秋期学術講演会, 2013年9月.
[36] 飯塚翔一, 水野雅文, 黒田弾, 橋本昌宜, 尾上孝雄, "適応的速度制御における連続時間マルコフ過程を用いた故障発生時間高速評価手法," 情報処理学会DAシンポジウム, 2013年8月.
[37] 郡浦宏明, Dawood Alnajjar, 密山幸男, 越智裕之, 今川隆司, 野田真一, 若林一敏, 橋本昌宜, 尾上孝雄, "動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討," 電子情報通信学会リコンフィギャラブルシステム研究会, number RECONF2013-8 , pages 41--46, 2013年5月.
[38] 郡浦宏明, Dawood Alnajjar, 密山幸男, 越智裕之, 今川隆司, 野田真一, 若林一敏, 橋本昌宜, 尾上孝雄, "C ベース設計に対応した信頼性可変粒度複合型再構成可能アーキテクチャ," LSIとシステムのワークショップ, 2013年5月.
[39] 原田諒, 密山幸男, 橋本昌宜, 尾上孝雄, "放射線起因一過性パルスが信頼性に与える影響の実験的評価," LSI とシステムのワークショップ, 2013年5月.
[40] 天木健彦, 橋本昌宜, 密山幸男, 尾上孝雄, "確率的動作モデルを用いたオシレータベース真性乱数生成回路のワーストケース設計手法," 電子情報通信学会 VLSI設計技術研究会, number VLD2012-154, pages 99--104, 2013年3月.
[41] 樋口裕磨, 橋本昌宜, 尾上孝雄, "オンチップセンサを用いたばらつき自己補償手法の検討," 電子情報通信学会 VLSI設計技術研究会, number VLD2012-138, pages 13--17, 2013年3月.
[42] 信田龍哉, 橋本昌宜, 尾上孝雄, "センサノード間静電容量結合に基づく距離推定に向けた電極形状の検討," 電子情報通信学会 回路とシステム研究会, number CAS2012-119, pages 131--136, 2013年3月.
[43] 原田諒, 密山幸男, 橋本昌宜, 尾上孝雄, "中性子起因一過性複数パルスの電源電圧及び基板バイアス依存性測定," 電子情報通信学会 VLSI設計技術研究会, number VLD2012-100, pages 237--241, 2012年11月.
[44] 郡浦宏明, 今川隆司, 密山幸男, 橋本昌宜, 尾上孝雄, "動的再構成機能を用いた故障回避手法の定量的信頼性評価," 電子情報通信学会 リコンフィギャラブルシステム研究会, number RECONF2012-59, pages 71--76, 2012年11月.
[45] 橋本昌宜, "低電力回路技術," センサマイクロマシンとその応用シンポジウムプログラム, 2012年10月.
[46] 上野美保, 橋本昌宜, 尾上孝雄, "電気的タイミング故障のデバッグ向けオンチップリアルタイム電源電圧センサ," 2012年電子情報通信学会ソサイエティ大会講演論文集, number A-3-6, 2012年9月.
[47] 安部晋一郎, 渡辺幸信, 原田諒, 橋本昌宜, 更田裕司, 上村大樹, "宇宙線中性子起因ソフトエラーに関するマルチセルアップセット解析," 応用物理学会秋期学術講演会, 2012年9月.
[48] 樋口裕磨, 新開健一, 橋本昌宜, R. Rao, S. Nassif, "感度可変リングオシレータを用いたデバイスパラメータばらつき推定," 情報処理学会DAシンポジウム, 2012年8月.
[49] 小谷憲, 増田弘生, 成木保文, 奥村隆昌, 城間誠, 金本俊幾, 古川且洋, 山中俊輝, 小笠原泰弘, 佐藤高史, 橋本昌宜, 黒川敦, 田中正和, "微細CMOSタイミング設計の新しいコーナー削減方法," 情報処理学会DAシンポジウム, pages 193--198, 2012年8月.
[50] 城間誠, 山中俊輝, 小笠原泰弘, 金本俊幾, 成木保文, 奥村隆昌, 増田弘生, 古川且洋, 佐藤高史, 橋本昌宜, 黒川敦, 田中正和, "微細プロセス(22nm世代)における配線コーナー設計手法の検討," 情報処理学会DAシンポジウム, pages 199--204, 2012年8月.
[51] 天木健彦, 橋本昌宜, 尾上孝雄, "ゆらぎ増幅回路を用いたオシレータベース物理乱数生成器," 電子情報通信学会 集積回路研究会, number ICD2011-118, pages 87--92, 2011年12月.
[52] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Conversion Based on Minimax," 電子情報通信学会 集積回路研究会, number ICD2011-121, pages 105--107, December 2011.
[53] 橋本昌宜, "超低電圧サブスレショルド回路設計," 電子情報通信学会 VLSI設計技術研究会, number VLD211-82, pages 173--178, 2011年11月.
[54] 佐方剛, 成木保文, 奥村隆昌, 金本俊幾, 増田弘生, 佐藤高史, 橋本昌宜, 古川且洋, 田中正和, 山中俊輝, "CMOSドライバ回路遅延のNBTI劣化ばらつき特性解析," 情報処理学会DAシンポジウム, 2011年9月.
[55] 亀田敏広, 郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄, "スキャンパスを用いたNBTI劣化抑制に関する一検討," 情報処理学会DAシンポジウム, pages 201--206, 2011年9月.
[56] 郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄, "動的再構成可能アーキテクチャによる故障回避機構の定量的信頼性評価," 電子情報通信学会 リコンフィギャラブルシステム研究会, number RECONF2011-6, pages 31--36, 2011年5月.
[57] 橋本昌宜, 更田裕司, "超低電圧サブスレショルド回路設計," 2011年電子情報通信学会総合大会講演論文集, 2011年3月.
[58] 高井康充, 橋本昌宜, 尾上孝雄, "電源ノイズに注目した電源遮断法の実機評価," 電子情報通信学会 集積回路研究会, number ICD2010-109, pages 75-80, 2010年12月.
[59] 橋本昌宜, "国際会議への論文の執筆ガイド 〜 VLSI設計技術分野での一考察 〜," 電子情報通信学会 VLSI設計技術研究会, number VLD2010-69, page 91, 2010年11月.
[60] 天木健彦, 橋本昌宜, 密山幸男, 尾上孝雄, "確率的動作モデルを用いたオシレータベース物理乱数生成器の設計手法," 情報処理学会システムLSI設計技術研究会, 2010年11月.
[61] 原田諒, 密山幸男, 橋本昌宜, 尾上孝雄, "高時間分解能を実現するSETパルス幅測定回路の提案," 電子情報通信学会 VLSI設計技術研究会, number VLD2010-55, pages 77--82, 2010年9月.
[62] 木村修太, 橋本昌宜, 尾上孝雄, "製造後性能補償のためのリーク・遅延相関考慮クラスタリング手法," 情報処理学会DAシンポジウム, pages 93--98, 2010年9月.
[63] 榎並孝司, 木村修太, 橋本昌宜, 尾上孝雄, "自己性能補償に向けたカナリアFF挿入手法," 情報処理学会DAシンポジウム, pages 227--232, 2010年9月.
[64] 増田弘生, 佐方剛, 佐藤高史, 橋本昌宜, 古川且洋, 田中正和, 山中俊輝, 金本俊幾, "RTNを考慮した回路特性ばらつき解析方法の検討," 情報処理学会DAシンポジウム, pages 209--214, 2010年9月.
[65] 橋本昌宜, "製造・環境ばらつきを考慮した統計的静的タイミング解析," エレクトロニクス実装学会 システムJisso-CAD/CAE研究会公開研究会, 2010年6月.
[66] 原田諒, 更田裕司, 密山幸男, 橋本昌宜, 尾上孝雄, "α線起因ソフトエラー測定 -SETパルス幅測定回路の提案および超低電圧SRAMのSEU耐性評価-," LSIとシステムのワークショップ, pages 212--214, 2010年5月.
[67] 郡浦宏明, D. Alnajjar, 高永勲, 今川隆司, 廣本正之, 密山幸男, 橋本昌宜, 越智裕之, 尾上孝雄, "柔軟な信頼性を実現する粗粒度再構成可能アーキテクチャ," LSIとシステムのワークショップ, pages 191--193, 2010年5月.
[68] 橋本昌宜, 更田裕司, 尾上孝雄, "製造ばらつきや環境変動を許容するサブスレッショルド回路設計," 2010年電子情報通信学会総合大会講演論文集, number AS-1-4, 2010年3月.
[69] 黒田弾, 更田裕司, 橋本昌宜, 尾上孝雄, "低消費エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価," 情報処理学会SLDM研究会, volume 2009-SLDM-141, number 19, 2009年10月.
[70] 新開健一, 橋本昌宜, "広範囲な製造・環境ばらつきに対応したゲート遅延モデル," 情報処理学会DAシンポジウム, pages 73--78, 2009年8月.
[71] 橋本昌宜, 榎並孝司, 新開健一, 二宮進有, 阿部慎也, "電源ノイズや製造ばらつきによるクロックジッタ・スキューを考慮した統計的タイミング解析," 情報処理学会DAシンポジウム, pages 79--84, 2009年8月.
[72] 郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄, "NBTIによる劣化予測におけるトランジスタ動作確率算出法の評価," 情報処理学会DAシンポジウム, pages 181--186, 2009年8月.
[73] 榎並孝司, 新開健一, 二宮進有, 阿部慎也, 橋本昌宜, "製造ばらつき、電源変動を統一的に取り扱った統計的静的タイミング解析手法," LSIとシステムのワークショップ, pages 283--285, 2009年5月.
[74] 佐方剛, 黒川敦, 奥村隆昌, 中島英斉, 増田弘生, 佐藤高史, 橋本昌宜, 蜂屋孝太郎, 古川且洋, 田中正和, 高藤浩資, 金本俊幾, "製造ばらつきに起因するリーク電流変動の低減アプローチ," 第22回 回路とシステム(軽井沢)ワークショップ, pages 444--449, 2009年4月. [120.pdf]
[75] 天木健彦, 橋本昌宜, 密山幸男, 尾上孝雄, "マルコフモデルによるオシレータサンプリング方式真性乱数生成器の乱数品質解析," 第22回 回路とシステム(軽井沢)ワークショップ, pages 474---479, 2009年4月. [121.pdf]
[76] 榎並孝司, 橋本昌宜, 佐藤高史, "電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法," 電子情報通信学会 VLSI設計技術研究会, number VLD2008-161, 2009年3月.
[77] 更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄, "サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証," 電子情報通信学会 VLSI設計技術研究会, number VLD2008-160, 2009年3月.
[78] 濱本浩一, 橋本昌宜, 密山幸男, 尾上孝雄, "レイアウトを考慮した基板バイアスクラスタリング手法," 電子情報通信学会 VLSI設計技術研究会, number VLD2008-159, 2009年3月.
[79] 高永勲, Dawood Alnajjar, 密山幸男, 橋本昌宜, 尾上孝雄, "柔軟な信頼性を実現する粗粒度再構成可能アーキテクチャの検討," 電子情報通信学会ディペンダブルコンピューティング研究会, number DC2008-41, 2008年11月.
[80] 更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄, "タイミングエラー予告を用いた適応的速度制御におけるタイミングエラー頻度と消費電力のトレードオフ解析," 情報処理学会DAシンポジウム, pages 217--222, 2008年8月.
[81] 濱本浩一, 更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄, "基板バイアス印加レイアウト方式の面積効率と速度制御性の評価 ," 電子情報通信学会 VLSI設計技術研究会, number VLD2008-14, 2008年6月.
[82] 渡辺慎吾, 橋本昌宜, 佐藤寿倫, "タイミング歩留まり改善を目的とする演算器カスケーディング," 先進的計算基盤システムシンポジウム(Symposium on Advanced Computing Systems and Infrastructures; SACSIS), pages 115--122, 2008年6月.
[83] 奥村隆昌, 黒川敦, 増田弘生, 金本俊幾, 佐藤高史, 橋本昌宜, 高藤浩資, 中島英斉, 小野信任, "Vth ばらつきに拠る出力遷移時間ばらつきの解析," 第21回 回路とシステム(軽井沢)ワークショップ, pages 299--304, 2008年4月.
[84] 増田弘生, 大川眞一, 黄田剛, 奥村隆昌, 黒川敦, 金本俊幾, 佐藤高史, 橋本昌宜, 高藤浩資, 中島英斉, 小野信任, "チップ内システマティックばらつきと回路スキュー特性相関," 第21回 回路とシステム(軽井沢)ワークショップ, pages 617--622, 2008年4月.
[85] 鉢田卓也, 松中栄貴, 白川功, 築山修治, 橋本昌宜, "nMOSダイナミック論理を用いた液晶駆動回路の設計手法," 電子情報通信学会 VLSI設計技術研究会, number VLD2007-148, 2008年3月.
[86] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "バス配線における誘導性クロストークノイズによる遅延変動の実測とノイズ重ね合わせ効果の検証," 電子情報通信学会 集積回路研究会, number ICD2007-176, 2008年3月.
[87] 大津誠, 高橋真吾, 築山修治, 橋本昌宜, 白川功, "nMOSレベルシフタ回路の性能比較手法について," 情報処理学会システムLSI設計技術研究会, number 2008-SLDM-134, pages 121--126, 2008年3月.
[88] 渡辺慎吾, 橋本昌宜, 佐藤寿倫, "性能歩留まり改善を目的とする演算器カスケーディングの提案," 第14回「ハイパフォーマンスコンピューティングとアーキテクチャの評価」に関する北海道ワークショップ(HOKKE-2008), number 2007-ARC-177 , pages 43--48, 2008年3月. [103.pdf]
[89] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "スタンダードセルで構成された電源ノイズ波形測定回路の提案," 電子情報通信学会 集積回路研究会, number CPM2007-131, ICD2007-142, pages 17--22, 2008年1月.
[90] 二宮進有, 橋本昌宜, "SSTAにおける空間的相関を持つ製造ばらつきのグリッドベースモデル化法の検討," 電子情報通信学会VLSI設計技術研究会, number VLD2007-91,DC2007-45, pages 13--17, 2007年11月.
[91] 橋本昌宜, "オンチップノイズ観測," 第11回システムLSIワークショップ, pages 149--157, 2007年11月.
[92] 橋本昌宜, "製造・環境ばらつきを考慮したタイミング検証技術," 電子情報通信学会 VLSI設計技術研究会, number VLD2007-65, pages 21--24, 2007年10月.
[93] 榎並孝司, 橋本昌宜, "統計的電源ノイズモデル化に適した適応的領域分割法," 2007年電子情報通信学会ソサイエティ大会講演論文集, number A-3-10, 2007年9月. [93.pdf]
[94] 阿部慎也, 橋本昌宜, 尾上孝雄, "製造ばらつきを考慮したメッシュ型クロック分配網のスキュー評価," 情報処理学会DAシンポジウム, pages 133-138, 2007年8月.
[95] 新開健一, 橋本昌宜, 尾上孝雄, "短距離ブロック内配線の自己発熱," 第20回 回路とシステム(軽井沢)ワークショップ, pages 7--12, 2007年4月. [83.pdf]
[96] 橋本昌宜, "製造・環境ばらつきと動的性能補償を考慮したタイミング検証に向けて," 第20回 回路とシステム(軽井沢)ワークショップ, pages 661--666, 2007年4月. [85.pdf]
[97] 榎並孝司, 二宮進有, 橋本昌宜, "電源ノイズの空間的相関を考慮した統計的タイミング解析," 第20回 回路とシステム(軽井沢)ワークショップ, pages 667--672, 2007年4月. [84.pdf]
[98] 中林太美世, 黒川敦, 増田弘生, 橋本昌宜, 佐藤高史, "45-65nmプロセスにおける遅延ばらつき特性の環境温度依存," 第20回 回路とシステム(軽井沢)ワークショップ, pages 691--696, 2007年4月. [86.pdf]
[99] 高藤浩資, 小林宏行, 小野信任, 増田弘生, 中島英斉, 奥村隆昌, 橋本昌宜, 佐藤高史, "統計的STAでのスルー依存性を考慮した遅延ばらつき計算手法の提案," 第20回 回路とシステム(軽井沢)ワークショップ, pages 709--714, 2007年4月. [87.pdf]
[100] 高橋真吾,築山修治,橋本昌宜,白川功, "液晶ディスプレイ用サンプリング回路の最適性について," 電子情報通信学会 VLSI設計技術研究会, number VLD2006-144, 2007年3月.
[101] Siriporn Jangsombatsiri, 橋本昌宜, 土谷亮, Haikun Zhu, Chun-Kuan Cheng, "シャントコンダクタンスを挿入したオンチップ伝送線路のアイパターン評価," 2007年電子情報通信学会総合大会講演論文集, number A-3-9, 2007年3月. [68.pdf]
[102] 濱本浩一, 橋本昌宜, 密山幸男, 尾上孝雄, "低電圧回路向け基板電位制御レイアウト方式の面積効率評価," 2007年電子情報通信学会総合大会講演論文集, number A-3-6, 2007年3月. [71.pdf]
[103] 阿部慎也, 橋本昌宜, 尾上孝雄, "メッシュ型クロック分配網のスキュー評価," 2007年電子情報通信学会総合大会講演論文集, number A-3-5, 2007年3月. [70.pdf]
[104] 更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄, "加算器を用いたsubthreshold 回路の設計指針の検討," 2007年電子情報通信学会総合大会講演論文集, number A-3-17, 2007年3月. [69.pdf]
[105] 二宮進有, 橋本昌宜, "空間的相関を考慮したSSTAにおける領域の分割数と精度," 2007年電子情報通信学会総合大会講演論文集, number A-3-1, 2007年3月. [67.pdf]
[106] 小笠原泰弘, 榎並孝司, 橋本昌宜, 佐藤高史、尾上孝雄, "電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現," 電子情報通信学会 集積回路研究会,, number ICD2006-174, 2007年1月.
[107] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測," 電子情報通信学会 集積回路研究会, number ICD2006-173, 2007年1月.
[108] Jangsombatsiri Siriporn, 橋本昌宜, 尾上孝雄, "シャントコンダクタンスを挿入したオンチップ伝送線路特性評価," 第十回シリコンアナログRF研究会, 2006年11月.
[109] 小笠原泰弘, 新開健一, 榎並孝司, 阿部慎也, 二宮進有, 橋本昌宜, "ナノメートル世代のVLSIタイミング設計技術の研究," 第10回システムLSIワークショップ, pages 195-198, 2006年11月.
[110] 新開健一, 橋本昌宜, 尾上孝雄, "短距離ブロック内配線の自己発熱問題の将来予測," 2006年電子情報通信学会ソサイエティ大会講演論文集, number A-3-14, 2006年9月. [72.pdf]
[111] 榎並孝司、橋本昌宜、尾上孝雄, "主成分分析による電源電圧変動の統計的モデル化手法," 情報処理学会DAシンポジウム, pages 205-210, 2006年7月.
[112] 小林宏行、小野信任、佐藤高史、岩井二郎、橋本昌宜, "統計的STA の精度検証手法," 情報処理学会DAシンポジウム, pages 7-12, 2006年7月.
[113] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測," 第19回 回路とシステム(軽井沢)ワークショップ, pages 5-10, 2006年4月. [73.pdf]
[114] 新開健一, 橋本昌宜, 黒川敦, 尾上孝雄, "電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル," 第19回 回路とシステム(軽井沢)ワークショップ, pages 559-564, 2006年4月. [75.pdf]
[115] 小林宏行, 小野信任, 佐藤高史, 岩井二郎, 橋本昌宜, "統計的STAの有効性の検証手法," 第19回 回路とシステム(軽井沢)ワークショップ, pages 553-558, 2006年4月. [74.pdf]
[116] 伊地知孝仁, 橋本昌宜,高橋真吾,築山修治,白川功, "画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術," 電子情報通信学会 VLSI設計技術研究会, number VLD2005-131, 2006年3月.
[117] 上村晋一朗, 土谷亮, 橋本昌宜, 小野寺秀俊, "ロードマップに準拠したSPICEトランジスタモデルの構築," 2006年電子情報通信学会総合大会講演論文集, number A-3-16, 2006年3月. [76.pdf]
[118] 榎並孝司, 橋本昌宜, 尾上孝雄, "電源ノイズ解析のための回路動作部表現法の評価," 2006年電子情報通信学会総合大会講演論文集, number A-3-15, 2006年3月. [77.pdf]
[119] 土谷亮, 新名亮規, 橋本昌宜、小野寺秀俊, "CMLを用いたオンチップ長距離高速信号伝送技術の開発," 第9回システムLSIワークショップ, pages 275-278, 2005年11月.
[120] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "LC共振器におけるMOSFETの抵抗成分を考慮した等価並列抵抗の見積もり," 2005年電子情報通信学会ソサイエティ大会講演論文集, number C-12-39, 2005年9月. [79.pdf]
[121] 高橋真吾,築山修治,橋本昌宜,白川功, "液晶ディスプレイ用サンプリング回路の設計手法について," 2005年電子情報通信学会ソサイエティ大会講演論文集, number A-3-4, 2005年9月. [78.pdf]
[122] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "誘導性・容量性クロストークノイズによる遅延変動の測定と評価," 電子情報通信学会 集積回路研究会, number ICD2005-74, 2005年8月.
[123] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線の伝達特性ノ基づく抽出周波数決定手法," 情報処理学会DAシンポジウム, pages 169-174, 2005年8月.
[124] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "SOIの基板抵抗率がLNAの性能に及ぼす影響の評価," 第四回シリコンアナログRF研究会, 2005年5月.
[125] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号伝送における終端抵抗決定手法," 第18回 回路とシステム(軽井沢)ワークショップ, pages 425-430, 2005年4月.
[126] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号伝送用配線の解析的性能評価," 電子情報通信学会 VLSI設計技術研究会, number VLD2004-145, 2005年3月.
[127] 高橋真吾,田治輝,築山修治,橋本昌宜,白川功, "液晶ディスプレイ用サンプリングスイッチの一設計法," エレクトロニクス実装学術講演大会, number 16B-12, 2005年3月.
[128] 土谷亮, 橋本昌宜, 小野寺秀俊, "実測と電磁界解析による基板損失の評価," 第三回シリコンアナログRF研究会, 2005年1月.
[129] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "LC型VCO最大発振周波数の実験的検討," 第三回シリコンアナログRF研究会, 2005年1月.
[130] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "システム液晶設計のための配線容量抽出手法," 電子情報通信学会 VLSI設計技術研究会(デザインガイア), number VLD2004-64, 2004年12月.
[131] 橋本昌宜, "ナノメートル世代のタイミング解析 -- 信号線・電源線ノイズ、ばらつき、熱への対応 --," 第8回システムLSIワークショップ, pages 191-200, 2004年11月.
[132] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "システム液晶に適した配線間容量抽出の検討," 2004年電子情報通信学会ソサイエティ大会講演論文集, number A-1-16, 2004年9月.
[133] 橋本昌宜, 小野寺秀俊, "微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応--," 2004年電子情報通信学会ソサイエティ大会講演論文集, 2004年9月.
[134] 土谷亮, 橋本昌宜, 小野寺秀俊, "基板および周辺信号配線が配線特性に及ぼす影響の実測," 第二回シリコンアナログRF研究会, 2004年8月.
[135] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "高周波CMOSデバイスモデルを用いたLCVCOの特性見積もりと実測," 第二回シリコンアナログRF研究会, 2004年8月.
[136] 村松篤, 橋本昌宜, 小野寺秀俊, "オンチップインダクタンスを考慮したLSI電源配線網解析," 情報処理学会DAシンポジウム, pages 277-282, 2004年7月.
[137] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線RL抽出におけるリターンパス選択手法," 情報処理学会DAシンポジウム, pages 175-180, 2004年7月.
[138] 佐藤高史, 市宮淳次, 小野信任, 蜂屋孝太郎, 橋本昌宜, "フロアプランにおけるオンチップ熱ばらつきの解析と対策," 情報処理学会DAシンポジウム, pages 133-138, 2004年7月.
[139] 金本俊幾, 阿久津滋聖, 中林太美世, 一宮敬弘, 蜂屋孝太郎, 石川博, 室本栄, 小林宏行, 橋本昌宜, 黒川敦, "遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価," 情報処理学会DAシンポジウム, pages 265-270, 2004年7月.
[140] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 ---," 第17回 回路とシステム(軽井沢)ワークショップ, pages 567-572, 2004年4月.
[141] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ伝送線路におけるリターン電流評価精度が信号波形に与える影響," 第一回シリコンアナログRF研究会, 2004年4月.
[142] 山口隼司, 橋本昌宜, 小野寺秀俊, "ゲート毎の電源電圧変動を考慮した静的遅延解析法," 電子情報通信学会 VLSI設計技術研究会, number ICD2003-236/VLD2003-143, 2004年3月.
[143] 村松篤, 橋本昌宜, 小野寺秀俊, "電源電圧変動に対するオンチップ配線インダクタンスの影響," 2004年電子情報通信学会総合大会講演論文集, number A-3-22, 2004年3月.
[144] 村松篤, 橋本昌宜, 小野寺秀俊, "電源配線の等価回路簡略化による電源解析高速化の検討," 平成15年度情報処理学会関西支部支部大会 VLSI研究会, number C-01, pages 169-172, 2003年11月.
[145] 宮崎崇仁, 橋本昌宜, 小野寺秀俊, "デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測 ーLC発振型VCOを用いたPLLの有効性ー," 電子情報通信学会集積回路研究会, number ICD2003-99, pages 29-34, 2003年9月.
[146] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号配線における波形歪みの影響," 2003年電子情報通信学会ソサイエティ大会講演論文集, number A-3-6, page 56, 2003年9月.
[147] 土谷亮, 橋本昌宜, 小野寺秀俊, "直交配線を持つオンチップ伝送線路の特性評価," 情報処理学会DAシンポジウム, pages 133-138, 2003年7月.
[148] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線R(f)L(f)C抽出のための代表周波数決定手法," 第16回 回路とシステム(軽井沢)ワークショップ, pages 61-66, 2003年4月.
[149] 宮崎崇仁, 新名亮規, 橋本昌宜, 小野寺秀俊, "オンチップオシロ用サンプルホールド回路の広周波数帯域化," 2003年電子情報通信学会総合大会講演論文集, number C-12-34, page 103, 2003年3月.
[150] 土谷亮, 橋本昌宜, 小野寺秀俊, "信号配線と下層配線との結合に対する直交配線の影響," 2003年電子情報通信学会総合大会講演論文集, number A-3-14, page 81, 2003年3月.
[151] 村松篤, 橋本昌宜, 小野寺秀俊, "オンチップデカップリング容量の最適寄生抵抗値の決定法," 2003年電子情報通信学会総合大会講演論文集, number A-3-13, page 80, 2003年3月.
[152] 橋本昌宜, "LSI物理設計におけるSignal Integrity問題," 情報処理学会関西支部VLSIシステム研究会平成14年度第3回研究会, 2003年3月.
[153] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "静的遅延解析のための等価ゲート入力波形導出法 --VDSMプロセスに起因する波形歪みへの対応--," 情報処理学会システムLSI設計技術研究会, number 2003-SLDM-108-20, pages 111-116, 2003年1月.
[154] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "容量性クロストークを考慮した高精度タイミング解析に関する研究," 平成14年度情報処理学会関西支部支部大会 VLSI研究会, number C-3, pages 113-114, 2002年11月.
[155] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスに起因する配線遅延変動の統計的予測手法," 2002年電子情報通信学会ソサイエティ大会講演論文集, number TA-2-4, pages 247-248, 2002年9月.
[156] 橋本昌宜, "京大版スタンダードセルライブラリ," VDEC LSI デザイナーフォーラム 2002, 2002年9月.
[157] 林宙輝, 橋本昌宜, 小野寺秀俊, "セルベース設計環境を用いた高性能データパス設計法の検討," 情報処理学会DAシンポジウム, pages 113-118, 2002年7月.
[158] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会DAシンポジウム, pages 149-154, 2002年7月.
[159] 山口隼司, 橋本昌宜, 小野寺秀俊, "IRドロップを考慮した電源線構造の最適化手法," 情報処理学会DAシンポジウム, pages 253-258, 2002年7月.
[160] 平松大輔, 土谷亮, 橋本昌宜, 小野寺秀俊, "長距離高速信号伝送を可能にするVLSI配線構造の検討," 情報処理学会DAシンポジウム, pages 155-160, 2002年7月.
[161] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスが配線遅延に及ぼす影響の定量的評価方法," 第15回 回路とシステム(軽井沢)ワークショップ, pages 493-498, 2002年4月.
[162] 藤森一憲, 橋本昌宜, 小野寺秀俊, "駆動力可変セルレイアウト生成システムによるスタンダードセルライブラリ開発," 電子情報通信学会VLSI設計技術研究会, number VLD2001-147/ICD2001-222, 2002年3月.
[163] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "ゲート出力波形導出時の誤差要因とその影響の評価," 2002年電子情報通信学会総合大会講演論文集, number A-3-3, page 82, 2002年3月.
[164] 土谷亮, 橋本昌宜, 小野寺秀俊, "LSI配線インダクタンスに対する直交配線の影響," 2002年電子情報通信学会総合大会講演論文集, number A-3-23, page 102, 2002年3月.
[165] 橋本昌宜, 高橋正郎, 小野寺秀俊, "ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法," 情報処理学会システムLSI設計技術研究会(デザインガイア), number SLDM103-6, pages 39-44, 2001年11月.
[166] 高橋正郎, 橋本昌宜, 小野寺秀俊, "波形重ね合せによるクロストーク遅延変動量の見積もり手法," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-9, page 63, 2001年9月.
[167] 橋本昌宜, 高橋正郎, 小野寺秀俊, "ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-8, page 62, 2001年9月.
[168] 土谷亮, 橋本昌宜, 小野寺秀俊, "長距離高速配線における RC モデルに基づく回路設計の限界," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-6, page 60, 2001年9月.
[169] 高橋正郎, 橋本昌宜, 小野寺秀俊, "隣接位置を考慮した解析的クロストークノイズ見積もり手法," 情報処理学会DAシンポジウム, pages 19-24, 2001年7月.
[170] 橋本昌宜, 高橋正郎, 小野寺秀俊, "隣接位置を考慮した解析的クロストークノイズモデル ---実回路への 適用---," 2001年電子情報通信学会総合大会講演論文集, number A-3-6, page 84, 2001年3月.
[171] 高橋正郎, 橋本昌宜, 小野寺秀俊, "隣接位置を考慮した解析的クロストークノイズモデル ---導出と評価 ---," 2001年電子情報通信学会総合大会講演論文集, number A-3-5, page 83, 2001年3月.
[172] 橋本昌宜, 小野寺秀俊, "パスバランス回路における遅延不確かさの統計的解析," 電子情報通信学会VLSI設計技術研究会(デザインガイア), number VLD2000-72, 2000年11月.
[173] 橋本昌宜, 小野寺秀俊, "パスバランス回路における遅延不確かさの統計的解析," 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-9, page 76, 2000年9月.
[174] 橋本昌宜, "オンデマンドライブラリを用いた最適LSI設計手法," VDEC LSI デザイナーフォーラム , 2000年8月.
[175] 橋本昌宜, 小野寺秀俊, "セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法," 情報処理学会DAシンポジウム, pages 185-190, 2000年7月.
[176] 橋本昌宜, 小野寺秀俊, "静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法," 第13回 回路とシステム(軽井沢)ワークショップ, pages 137-142, 2000年4月.
[177] 橋本昌宜, 橋本鉄太郎, 西川亮太, 福田大輔, 黒田慎介, 菅俊介, 神原弘之, 小野寺秀俊, "オンデマンドライブラリを用いたシステムLSI詳細設計手法," 電子情報通信学会VLSI設計技術研究会, number VLD99-112/ICD99-269, 2000年3月.
[178] 橋本昌宜, 小野寺秀俊, "静的統計遅延解析を用いた最悪遅延時間計算手法," 2000年電子情報通信学会総合大会講演論文集, number A-3-13, page 81, 2000年3月.
[179] 橋本昌宜, 橋本鉄太郎,西川亮太,福田大輔,黒田慎介,菅俊介,神原弘之,小野寺秀俊, "オンデマンドライブラリを用いたシステムLSI詳細設計手法," 第3回 システムLSI琵琶湖ワークショップ, pages 279-281, 1999年11月.
[180] 橋本昌宜, 小野寺秀俊, "スタンダードセルライブラリの駆動能力種類の追加による消費電力削減効果の検討," 1999年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-9, page 52, 1999年9月.
[181] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 ---レイアウト設計への適用---," 1998年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-5, 1998年9月.
[182] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法," 情報処理学会DAシンポジウム, pages 269-274, 1998年7月.
[183] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "論理シミュレーションを用いた消費電力見積もりの高精度化手法," 1998年電子情報通信学会総合大会講演論文集, number A-3-5, page 91, 1998年3月.
[184] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "入力端子接続最適化による遅延時間と消費電力の最適化手法," 1997年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-15, page 67, 1997年9月.
[185] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "入力端子接続最適化による消費電力削減手法," 情報処理学会DAシンポジウム, pages 99-104, 1997年7月.
研究会・全国大会等
[1] 西孝将, 増田豊, 橋本昌宜, "FPGAを用いた動的電源ノイズ下でのエラー予告FFの動作検証," 電子情報通信学会総合大会講演論文集, 採録済.
[2] 山田詩門, 劉載勲, 橋本昌宜, "スパイキングニューラルネットワークの教師あり学習法の検討," 電子情報通信学会総合大会講演論文集, 採録済.
[3] 橋本昌宜, "高エネルギー効率コンピューティングを実現するビアスイッチFPGA," 電子情報通信学会VLSI設計技術研究会, 採録済.
[4] 白井僚, 陳沛豪, 清水綾平, 橋本昌宜, "単一アンカーコイルによる直流磁界を用いた位置推定手法の検討," 電子情報通信学会 回路とシステム研究会, 2018年12月.
[5] 清水綾平, 白井僚, 陳沛豪, 橋本昌宜, "地磁気センサアレイの時系列データを用いた動き予測の検討," 電子情報通信学会 回路とシステム研究会, 2018年12月.
[6] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," Work in Progress Session, Design Automation Conference (DAC), June 2016.
[7] M. Hashimoto, M. Ueno, and T. Onoye, "Real-Time Supply Voltage Sensor for Trace-Based Fault Localization," Poster Session, International Test Conference (ITC), October 2014.
[8] M. Hashimoto, "Reliability Challenge for Exa-Scale Near-Threshold Computing -- Soft Error Perspective --," Elevator Talk Session, International Test Conference (ITC), September 2013.
[9] M. Hashimoto, "Adaptive Speed Control and Its Extremely-Low Error Rate Estimation," Elevator Talk Session, International Test Conference (ITC), November 2012.
[10] 橋本昌宜, "超低電圧SRAMにおける中性子起因ソフトエラーの評価," ソフトエラー(などのLSIにおける放射線効果)に関する第1回勉強会, 2011年9月.
著書
[1] E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M. Hashimoto, T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, and M. Sugihara, "Radiation-Induced Soft Errors," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.
[2] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, and M. Tada, "Applications of Reconfigurable Processors as Embedded Automatons in the Iot Sensor Networks in Space," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.
[3] T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, and J. Yao, "Time-Dependent Degradation in Device Characteristics and Countermeasures by Design," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.
[4] M. Hashimoto and R. Nair, Power Integrity for Nanoscale Integrated Systems, McGraw-Hill Professional,, 2014.
[5] M. Hashimoto and R. Nair, "Power Integrity Management in Integrated Circuits and Systems," Book chapter, Power Integrity Analysis and Management for Integrated Circuits, Prentice Hall PTR, May 2010.
[6] R. Nair, M. Hashimoto, and N. Srivastava, "Ic Power Integrity and Optimal Power Delivery," Book chapter, Power Integrity Analysis and Management for Integrated Circuits, Prentice Hall PTR, May 2010.
解説
[1] 橋本昌宜, "宇宙線ミューオンが電子機器の誤作動を引き起こす," Isotope News, number 761, 2019年2月. [pdf]
[2] 佐藤高史, 橋本昌宜, "経時劣化概説," 信頼性学会誌, volume 35, number 8, pages 457--458, 2013年12月.
[3] 橋本昌宜, "超低電力サブスレッショルド回路設計技術 ," IEICE Fundamentals Review, pages 30--37, 2013年7月. [189.pdf]
[4] 橋本昌宜, "遅延ばらつきを考慮したVLSIタイミング検証," エレクトロニクス実装学会誌, volume 11, number 3, pages 182--185, 2008年5月.