Academic Journal
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H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, T. Sakamoto
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Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture
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IEEE Embedded Systems Letters
| 10(4)
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119 -- 122
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December 2018
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| desc
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Academic Journal
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H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, M. Hashimoto
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Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars
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IEEE Transactions on VLSI Systems
| 26(12)
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2723--2736
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December 2018
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| pdf
|
Academic Journal
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K. Mitsunari, J. Yu, T. Onoye, M. Hashimoto
|
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
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IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E101-A(9)
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1298--1307
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September 2018
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| pdf
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International Conference
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, , , , , , , , , , M. Hashimoto
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A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --
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Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
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August 2025
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| pdf
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International Conference
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M. Hashimoto, , N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, , H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi
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Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications
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Technical Digest of International Solid-State Circuits Conference (ISSCC)
|
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502--503
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February 2020
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| pdf
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International Conference
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, J. Yu, M. Hashimoto
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A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform
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Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
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October 2019
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International Conference
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K. Mitsunari, J. Yu, M. Hashimoto
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Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features
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Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)
|
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55-58
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November 2018
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| pdf
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International Conference
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J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto
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A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch
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Proceedings of International Conference on Field Programmable Logic and Applications (FPL)
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|
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August 2016
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| pdf
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International Conference
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T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
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A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture
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Proceedings of International Conference on Field Programmable Logic and Applications (FPL)
|
|
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August 2012
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| 170.pdf
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International Conference
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H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
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Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture
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Proceedings of International Conference on Field Programmable Logic and Applications (FPL)
|
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189--194
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September 2011
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| 162.pdf
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International Conference
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D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
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MTTF Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability
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IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)
|
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March 2011
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International Conference
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D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye
|
Soft Error Resilient VLSI Architecture for Signal Processing
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Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
|
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183--186
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December 2009
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| 142.pdf
|
