この検索内の頻出タグ: architecture^:4 reconfigurable^:4 avoidance^:3 coarse-grained^:3 delay^:3 estimation^:3 fault^:3 nbti^:3 simulation^:3 soft^:3 error^:2 irradiation^:2 measurement^:2 methodology^:2 mitigation^:2 neutron^:2 predictive^:2 probability^:2 random^:2 reliability^:2 scan-in^:2 ser^:2 standby^:2 stress^:2 terrestrial^:2 vectors^:2 0.8-v^:1 110-na^:1 achieved^:1 alpha^:1

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論文誌

[1] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology Based on Simulation Coupled with One-Time Neutron Irradiation Testing," IEEE Transactions on Nuclear Science, volume 70, number 8, 1652 -- 1657, August 2023. [pdf]

[2] A. Lopez, Y. Okoshi, M. Hashimoto, M. Motomura, and J. Yu, "Recurrent Residual Networks Contain Stronger Lottery Tickets," IEEE Access, volume 11, 16588 - 16604, February 2023. [pdf]

[3] M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, and Y. Watanabe, "Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation (Invited)," Integration, the VLSI Journal, volume 69, pages 161--179, November 2019. [pdf]

[4] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2518--2529, December 2014. [210.pdf]

[5] H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1468--1482, July 2014. [201.pdf]

[6] H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1483--1491, July 2014. [202.pdf]

[7] D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture," IEEE Transactions on VLSI Systems, volume 21, number 12, 2165 -- 2178, December 2013. [177.pdf]

[8] T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices," IEICE Trans. on Information and Systems, volume E96-D, number 8, pages 1624--1631, August 2013. [191.pdf]

[9] I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, "A 0.8-V 110-nA CMOS Current Reference Circuit Using Subthreshold Operation," IEICE Electronics Express (ELEX), volume 10, number 4, March 2013. [182.pdf]

[10] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Stress Probability Computation for Estimating NBTI-Induced Delay Degradation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 12, pages 2545--2553, December 2011. [166.pdf]

[11] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜, "遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会論文誌, volume 44, number 5, pages 1301-1310, 2003年5月. [21.pdf]

国際会議

[1] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology with Simulation and Single-Source Irradiation Applicable to Diverse Neutron Sources," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022.

[2] M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 14--15, January 2015. [213.pdf]

[3] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, and T. Onoye, "Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design," Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2013. [199.pdf]

[4] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 313--316, November 2013. [196.pdf]

[5] T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2012. [170.pdf]

[6] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 189--194, September 2011. [162.pdf]

[7] T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "NBTI Mitigation by Giving Random Scan-In Vectors During Standby Mode," Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pages 152--161, September 2011.

[8] D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "MTTF Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability," IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.

[9] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Study on Delay Degrading Estimation Due to NBTI with Circuit/Instance/Transistor-Level Stress Probability Consideration," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 646--651, March 2010. [137.pdf]

[10] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Soft Error Resilient VLSI Architecture for Signal Processing," Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 183--186, December 2009. [142.pdf]

[11] D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 186--192, August 2009. [133.pdf]

[12] Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 236--241, March 2009.

[13] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability," Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.

[14] T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, and M. Hashimoto, "Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 149-155, January 2003. [40.pdf]

国内会議(査読付き)

[1] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会DAシンポジウム, pages 149-154, 2002年7月.

[2] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスが配線遅延に及ぼす影響の定量的評価方法," 第15回 回路とシステム(軽井沢)ワークショップ, pages 493-498, 2002年4月.

研究会・全国大会等

[1] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスに起因する配線遅延変動の統計的予測手法," 2002年電子情報通信学会ソサイエティ大会講演論文集, number TA-2-4, pages 247-248, 2002年9月.

著書

[1] E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M. Hashimoto, T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, and M. Sugihara, "Radiation-Induced Soft Errors," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.