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138 件の該当がありました． : このページのURL : HTML

論文誌: [1] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation," Japanese Journal of Applied Physics, volume 61, number SM0804, October 2022. [pdf]; [2] N. Banno, K. Okamoto, N. Iguchi, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, "Low-Power Crossbar Switch with Two-Varistors Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA," IEEE Transactions on Electron Devices, volume 66, number 8, pages 3331--3336, August 2019. [pdf]; [3] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, and T. Sakamoto, "Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture," IEEE Embedded Systems Letters, volume 10, number 4, 119 -- 122, December 2018. [desc]; [4] H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, and M. Hashimoto, "Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars," IEEE Transactions on VLSI Systems, volume 26, number 12, pages 2723--2736, December 2018. [pdf]; [5] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2518--2529, December 2014. [210.pdf]; [6] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," IEICE Trans. on Information and Systems, volume E91-D, number 3, pages 655--660, March 2008. [101.pdf]; [7] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 12, pages 2661-2668, December 2007. [95.pdf]; [8] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling," IEICE Trans. on Electronics, volume E90-C, number 6, pages 1267-1273, June 2007. [88.pdf]; [9] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3585-3593, December 2006. [2.pdf]; [10] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006. [3.pdf]; [11] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation in H-Tree Structure," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pp.3375-3381, December 2005. [6.pdf]; [12] A. Muramatsu, M. Hashimoto, and H. Onodera, "Effects of On-Chip Inductance on Power Distribution Grid," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3564-3572, December 2005. [7.pdf]; [13] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment for Minimizing Supply Voltage Drop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A,, number 12, pages 3429-3436, December 2005. [8.pdf]; [14] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 4, pages 885-891, April 2005. [11.pdf]; [15] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL," IEICE Trans. on Electronics, volume E88-C, number 3, pages 437-444, March 2005. [89.pdf]; [16] M. Hashimoto and H. Onodera, "Crosstalk Noise Optimization by Post-Layout Transistor Sizing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E87-A, number 12, pages 3251-3257, December 2004. [12.pdf]; [17] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 23, number 4, pages 498-508, April 2004. [20.pdf]; [18] M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk Noise Estimation for Generic RC Trees," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 2965-2973, December 2003. [13.pdf]; [19] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 2942-2951, December 2003. [14.pdf]; [20] M. Hashimoto, Y. Hayashi, and H. Onodera, "Experimental Study on Cell-Base High-Performance Datapath Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 3204-3207, December 2003. [15.pdf]; [21] M. Hashimoto and H. Onodera, "Increase in Delay Uncertainty by Performance Optimization," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 12, pages 2799-2802, December 2002. [16.pdf]; [22] 土谷亮, 橋本昌宜, 小野寺秀俊, "VLSI配線の伝送線路特性を考慮した駆動力決定手法," 情報処理学会論文誌, volume 43, number 5, pages 1338--1347, 2002年5月. [63.pdf]; [23] M. Hashimoto and H. Onodera, "Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E84-A, number 11, pages 2769-2777, November 2001. [17.pdf]; [24] M. Hashimoto and H. Onodera, "A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E83-A, number 12, pages 2558-2568, December 2000. [18.pdf]; [25] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法," 情報処理学会論文誌, volume 40, number 4, pages 1707-1716, 1999年4月.; [26] M. Hashimoto, H. Onodera, and K. Tamaru, "A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E82-A, number 1, pages 159-166, January 1999. [19.pdf]
国際会議: [1] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), pages 502--503, February 2020. [pdf]; [2] N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch for a Highly-Dense Reconfigurable Logic," Technical Digest of IEEE International Electron Devices Meeting (IEDM), December 2016. [231.PDF]; [3] H.-Y. Su, B.-S. Wang, S.-Y. Hsieh, Y.-L. Li, I-H. Wu, C.-C. Wu, W.-C. Shih, H. Onodera, and M. Hashimoto, "Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2016.; [4] H. Hihara, A. Iwasaki, N. Tamagawa, M. Kuribayashi, M. Hashimoto, Y. Mitsuyama, H. Ochi, H. Onodera, H. Kanbara, K. Wakabayashi, and T. Sugibayashi, "Novel Processor Architecture for Onboard Infrared Sensors (Invited)," Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV, volume 9973, August 2016.; [5] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2016. [pdf]; [6] R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.; [7] N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-Outs," Technical Digest of IEEE International Electron Devices Meeting (IEDM), pages 32--35, December 2015. [225.PDF]; [8] M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 14--15, January 2015. [213.pdf]; [9] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 313--316, November 2013. [196.pdf]; [10] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227-230, May 2006. [65.pdf]; [11] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction at a Single Representative Frequency," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 515-520, January 2006. [30.pdf]; [12] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction," In Proceedings of International Workshop on Compact Modeling (IWCM), pages 51-56, January 2006.; [13] T. Kouno, M. Hashimoto, and H. Onodera, "Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 453-456, November 2005. [52.pdf]; [14] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip High-Throughput Global Signaling," In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 79-82, October 2005. [50.pdf]; [15] S. Uemura, T. Miyazaki, M. Hashimoto, and H. Onodera, "Estimation of Maximum Oscillation Frequency for CMOS LCVCOs," In Proceedings of IEEJ International Analog VLSI Workshop, October 2005.; [16] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 613-616, September 2005. [27.pdf]; [17] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer," In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 201-202, May 2005. [49.pdf]; [18] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics," In Proceedings of International Meeting for Future of Electron Devices, Kansai, pages 33-34, April 2005.; [19] A. Muramatsu, M. Hashimoto, and H. Onodera, "Effects of On-Chip Inductance on Power Distribution Grid," In Proceedings of International Symposium on Physical Design (ISPD), pages 63-69, April 2005. [46.pdf]; [20] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation in H-Tree Structure," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 402-407, March 2005. [51.PDF]; [21] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 723-728, January 2005. [31.pdf]; [22] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1098-1101, January 2005. [32.pdf]; [23] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Return Path Selection for Loop RL Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1078-1081, January 2005. [33.pdf]; [24] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um CMOS Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), D9-D10, January 2005. [35.pdf]; [25] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip Global Signaling," In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), pages 87-100, November 2004.; [26] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 814-820, November 2004. [41.pdf]; [27] M. Hashimoto, A. Tsuchiya, and H. Onodera, "On-Chip Global Signaling by Wave Pipelining," In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 311-314, October 2004. [56.pdf]; [28] A. Muramatsu, M. Hashimoto, and H. Onodera, "LSI Power Network Analysis with On-Chip Wire Inductance," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 55-60, October 2004.; [29] T. Sato, M. Hashimoto, and H. Onodera, "An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 66-72, October 2004.; [30] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 214-219, October 2004.; [31] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL," In IEEJ International Analog VLSI Workshop, pages 45-50, October 2004.; [32] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 489-492, September 2004. [66.pdf]; [33] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Optimization of CMOS Current Mode Logic Dividers," In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pages 434-435, August 2004. [55.pdf]; [34] M. Hashimoto, K. Fujimori, and H. Onodera, "Automatic Generation of Standard Cell Library in VDSM Technologies," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 36-41, March 2004. [53.PDF]; [35] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 691-696, January 2004. [37.pdf]; [36] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Comparison of PLLs for Clock Generation Using Ring Oscillator VCO and LC Oscillator in a Digital CMOS Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 545-546, January 2004. [36.pdf]; [37] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 169-175, November 2003. [42.pdf]; [38] M. Hashimoto, Y. Yamada, and H. Onodera, "Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis," In Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD), pages 18-23, April 2003. [45.pdf]; [39] Y. Yamada, M. Hashimoto, and H. Onodera, "Slew Calculation Against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 280-287, April 2003.; [40] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Frequency Determination for Interconnect RLC Extraction," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 288-293, April 2003.; [41] M. Hashimoto, K. Fujimori, and H. Onodera, "Standard Cell Libraries with Various Driving Strength Cells for 0.13, 0.18 and 0.35um Technologies," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 589-590, January 2003. [38.pdf]; [42] M. Hashimoto, D. Hiramatsu, A. Tsuchiya, and H. Onodera, "Interconnect Structures for High-Speed Long-Distance Signal Transmission," In Proceedings of IEEE International ASIC/SOC Conference, pages 426-430, September 2002. [57.pdf]; [43] M. Hashimoto, Y. Hayashi, and H. Onodera, "Experimental Study on Cell-Base High-Performance Datapath Design," In Proceedings of IEEE/ACM International Workshop on Logic & Synthesis (IWLS), pages 283-287, June 2002.; [44] M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk Noise Optimization by Post-Layout Transistor Sizing," In Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD), pages 126-130, April 2002. [43.pdf]; [45] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 377-381, October 2001.; [46] M. Takahashi, M. Hashimoto, and H. Onodera, "Crosstalk Noise Estimation for Generic RC Trees," In Proceedings of International Conference on Computer Design (ICCD), pages 110-116, September 2001. [58.pdf]; [47] H. Onodera, M. Hashimoto, and T. Hashimoto, "ASIC Design Methodology with On-Demand Library Generation," In Proceedings of Symposium on VLSI Circuits, pages 57-60, June 2001. [59.pdf]; [48] M. Hashimoto and H. Onodera, "Increase in Delay Uncertainty by Performance Optimization," In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), volume V, pages 379-382, May 2001. [60.pdf]; [49] M. Hashimoto and H. Onodera, "Post-Layout Transistor Sizing for Power Reduction in Cell-Based Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 359-365, January 2001. [39.pdf]; [50] M. Hashimoto and H. Onodera, "A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing," In Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 34-37, December 2000.; [51] T. Iwahashi, T. Shibayama, M. Hashimoto, K. Kobayashi, and H. Onodera, "Vector Quantization Processor for Mobile Video Communication," In Proceedings of IEEE International ASIC/SOC Conference, pages 75-79, September 2000. [61.pdf]; [52] M. Hashimoto and H. Onodera, "A Performance Optimization Method by Gate Sizing Using Statistical Static Timing Analysis," In Proceedings of ACM International Symposium on Physical Design (ISPD), pages 111-116, April 2000. [44.pdf]; [53] M. Hashimoto and H. Onodera, "A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis," In Proceedings of the Ninth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 115-121, April 2000.; [54] M. Hashimoto, H. Onodera, and K. Tamaru, "Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design," In Proceedings of the 36th IEEE/ACM Design Automation Conference (DAC), pages 446-451, June 1999. [47.pdf]; [55] M. Hashimoto, H. Onodera, and K. Tamaru, "A Power Optimization Method Considering Glitch Reduction by Gate Sizing," In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 221-226, August 1998. [48.pdf]; [56] M. Hashimoto, H. Onodera, and K. Tamaru, "Input Reordering for Power and Delay Optimization," In Proceedings of IEEE International ASIC Conference and Exhibit, pages 194-198, September 1997. [62.pdf]
国内会議(査読付き): [1] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線の伝達特性ﾉ基づく抽出周波数決定手法," 情報処理学会DAシンポジウム, pages 169-174, 2005年8月.; [2] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号伝送における終端抵抗決定手法," 第18回回路とシステム(軽井沢)ワークショップ, pages 425-430, 2005年4月.; [3] 村松篤, 橋本昌宜, 小野寺秀俊, "オンチップインダクタンスを考慮したLSI電源配線網解析," 情報処理学会DAシンポジウム, pages 277-282, 2004年7月.; [4] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線RL抽出におけるリターンパス選択手法," 情報処理学会DAシンポジウム, pages 175-180, 2004年7月.; [5] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 ---," 第17回回路とシステム(軽井沢)ワークショップ, pages 567-572, 2004年4月.; [6] 土谷亮, 橋本昌宜, 小野寺秀俊, "直交配線を持つオンチップ伝送線路の特性評価," 情報処理学会DAシンポジウム, pages 133-138, 2003年7月.; [7] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線R(f)L(f)C抽出のための代表周波数決定手法," 第16回回路とシステム(軽井沢)ワークショップ, pages 61-66, 2003年4月.; [8] 林宙輝, 橋本昌宜, 小野寺秀俊, "セルベース設計環境を用いた高性能データパス設計法の検討," 情報処理学会DAシンポジウム, pages 113-118, 2002年7月.; [9] 山口隼司, 橋本昌宜, 小野寺秀俊, "IRドロップを考慮した電源線構造の最適化手法," 情報処理学会DAシンポジウム, pages 253-258, 2002年7月.; [10] 平松大輔, 土谷亮, 橋本昌宜, 小野寺秀俊, "長距離高速信号伝送を可能にするVLSI配線構造の検討," 情報処理学会DAシンポジウム, pages 155-160, 2002年7月.; [11] 高橋正郎, 橋本昌宜, 小野寺秀俊, "隣接位置を考慮した解析的クロストークノイズ見積もり手法," 情報処理学会DAシンポジウム, pages 19-24, 2001年7月.; [12] 橋本昌宜, 小野寺秀俊, "セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法," 情報処理学会DAシンポジウム, pages 185-190, 2000年7月.; [13] 橋本昌宜, 小野寺秀俊, "静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法," 第13回回路とシステム(軽井沢)ワークショップ, pages 137-142, 2000年4月.; [14] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法," 情報処理学会DAシンポジウム, pages 269-274, 1998年7月.; [15] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "入力端子接続最適化による消費電力削減手法," 情報処理学会DAシンポジウム, pages 99-104, 1997年7月.
研究会・全国大会等: [1] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," Work in Progress Session, Design Automation Conference (DAC), June 2016.; [2] 上村晋一朗, 土谷亮, 橋本昌宜, 小野寺秀俊, "ロードマップに準拠したSPICEトランジスタモデルの構築," 2006年電子情報通信学会総合大会講演論文集, number A-3-16, 2006年3月. [76.pdf]; [3] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "LC共振器におけるMOSFETの抵抗成分を考慮した等価並列抵抗の見積もり," 2005年電子情報通信学会ソサイエティ大会講演論文集, number C-12-39, 2005年9月. [79.pdf]; [4] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "SOIの基板抵抗率がLNAの性能に及ぼす影響の評価," 第四回シリコンアナログRF研究会, 2005年5月.; [5] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号伝送用配線の解析的性能評価," 電子情報通信学会 VLSI設計技術研究会, number VLD2004-145, 2005年3月.; [6] 土谷亮, 橋本昌宜, 小野寺秀俊, "実測と電磁界解析による基板損失の評価," 第三回シリコンアナログRF研究会, 2005年1月.; [7] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "LC型VCO最大発振周波数の実験的検討," 第三回シリコンアナログRF研究会, 2005年1月.; [8] 橋本昌宜, 小野寺秀俊, "微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応--," 2004年電子情報通信学会ソサイエティ大会講演論文集, 2004年9月.; [9] 土谷亮, 橋本昌宜, 小野寺秀俊, "基板および周辺信号配線が配線特性に及ぼす影響の実測," 第二回シリコンアナログRF研究会, 2004年8月.; [10] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "高周波CMOSデバイスモデルを用いたLCVCOの特性見積もりと実測," 第二回シリコンアナログRF研究会, 2004年8月.; [11] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ伝送線路におけるリターン電流評価精度が信号波形に与える影響," 第一回シリコンアナログRF研究会, 2004年4月.; [12] 山口隼司, 橋本昌宜, 小野寺秀俊, "ゲート毎の電源電圧変動を考慮した静的遅延解析法," 電子情報通信学会 VLSI設計技術研究会, number ICD2003-236/VLD2003-143, 2004年3月.; [13] 村松篤, 橋本昌宜, 小野寺秀俊, "電源電圧変動に対するオンチップ配線インダクタンスの影響," 2004年電子情報通信学会総合大会講演論文集, number A-3-22, 2004年3月.; [14] 村松篤, 橋本昌宜, 小野寺秀俊, "電源配線の等価回路簡略化による電源解析高速化の検討," 平成15年度情報処理学会関西支部支部大会 VLSI研究会, number C-01, pages 169-172, 2003年11月.; [15] 宮崎崇仁, 橋本昌宜, 小野寺秀俊, "デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測ーLC発振型VCOを用いたPLLの有効性ー," 電子情報通信学会集積回路研究会, number ICD2003-99, pages 29-34, 2003年9月.; [16] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号配線における波形歪みの影響," 2003年電子情報通信学会ソサイエティ大会講演論文集, number A-3-6, page 56, 2003年9月.; [17] 宮崎崇仁, 新名亮規, 橋本昌宜, 小野寺秀俊, "オンチップオシロ用サンプルホールド回路の広周波数帯域化," 2003年電子情報通信学会総合大会講演論文集, number C-12-34, page 103, 2003年3月.; [18] 土谷亮, 橋本昌宜, 小野寺秀俊, "信号配線と下層配線との結合に対する直交配線の影響," 2003年電子情報通信学会総合大会講演論文集, number A-3-14, page 81, 2003年3月.; [19] 村松篤, 橋本昌宜, 小野寺秀俊, "オンチップデカップリング容量の最適寄生抵抗値の決定法," 2003年電子情報通信学会総合大会講演論文集, number A-3-13, page 80, 2003年3月.; [20] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "静的遅延解析のための等価ゲート入力波形導出法　--VDSMプロセスに起因する波形歪みへの対応--," 情報処理学会システムLSI設計技術研究会, number 2003-SLDM-108-20, pages 111-116, 2003年1月.; [21] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "容量性クロストークを考慮した高精度タイミング解析に関する研究," 平成14年度情報処理学会関西支部支部大会 VLSI研究会, number C-3, pages 113-114, 2002年11月.; [22] 藤森一憲, 橋本昌宜, 小野寺秀俊, "駆動力可変セルレイアウト生成システムによるスタンダードセルライブラリ開発," 電子情報通信学会VLSI設計技術研究会, number VLD2001-147/ICD2001-222, 2002年3月.; [23] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "ゲート出力波形導出時の誤差要因とその影響の評価," 2002年電子情報通信学会総合大会講演論文集, number A-3-3, page 82, 2002年3月.; [24] 土谷亮, 橋本昌宜, 小野寺秀俊, "LSI配線インダクタンスに対する直交配線の影響," 2002年電子情報通信学会総合大会講演論文集, number A-3-23, page 102, 2002年3月.; [25] 橋本昌宜, 高橋正郎, 小野寺秀俊, "ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法," 情報処理学会システムLSI設計技術研究会(デザインガイア), number SLDM103-6, pages 39-44, 2001年11月.; [26] 高橋正郎, 橋本昌宜, 小野寺秀俊, "波形重ね合せによるクロストーク遅延変動量の見積もり手法," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-9, page 63, 2001年9月.; [27] 橋本昌宜, 高橋正郎, 小野寺秀俊, "ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-8, page 62, 2001年9月.; [28] 土谷亮, 橋本昌宜, 小野寺秀俊, "長距離高速配線における RC モデルに基づく回路設計の限界," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-6, page 60, 2001年9月.; [29] 橋本昌宜, 高橋正郎, 小野寺秀俊, "隣接位置を考慮した解析的クロストークノイズモデル ---実回路への適用---," 2001年電子情報通信学会総合大会講演論文集, number A-3-6, page 84, 2001年3月.; [30] 高橋正郎, 橋本昌宜, 小野寺秀俊, "隣接位置を考慮した解析的クロストークノイズモデル ---導出と評価 ---," 2001年電子情報通信学会総合大会講演論文集, number A-3-5, page 83, 2001年3月.; [31] 橋本昌宜, 小野寺秀俊, "パスバランス回路における遅延不確かさの統計的解析," 電子情報通信学会VLSI設計技術研究会(デザインガイア), number VLD2000-72, 2000年11月.; [32] 橋本昌宜, 小野寺秀俊, "パスバランス回路における遅延不確かさの統計的解析," 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-9, page 76, 2000年9月.; [33] 橋本昌宜, 橋本鉄太郎, 西川亮太, 福田大輔, 黒田慎介, 菅俊介, 神原弘之, 小野寺秀俊, "オンデマンドライブラリを用いたシステムLSI詳細設計手法," 電子情報通信学会VLSI設計技術研究会, number VLD99-112/ICD99-269, 2000年3月.; [34] 橋本昌宜, 小野寺秀俊, "静的統計遅延解析を用いた最悪遅延時間計算手法," 2000年電子情報通信学会総合大会講演論文集, number A-3-13, page 81, 2000年3月.; [35] 橋本昌宜, 小野寺秀俊, "スタンダードセルライブラリの駆動能力種類の追加による消費電力削減効果の検討," 1999年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-9, page 52, 1999年9月.; [36] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 ---レイアウト設計への適用---," 1998年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-5, 1998年9月.; [37] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "論理シミュレーションを用いた消費電力見積もりの高精度化手法," 1998年電子情報通信学会総合大会講演論文集, number A-3-5, page 91, 1998年3月.; [38] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "入力端子接続最適化による遅延時間と消費電力の最適化手法," 1997年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-15, page 67, 1997年9月.
著書: [1] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, and T. Sakamoto, "Atomic Switch FPGA: Application for IoT Sensing Systems in Space," Book Chapter, Atomic Switch, Springer, March 2020.; [2] E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M. Hashimoto, T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, and M. Sugihara, "Radiation-Induced Soft Errors," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.; [3] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, and M. Tada, "Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.