この検索内の頻出タグ: reconfigurable^:9 architecture^:5 avoidance^:3 coarse-grained^:3 fault^:3 highly-dense^:3 crossbar^:2 devices^:2 overlay^:2 predictive^:2 reliability^:2 via-switch^:2 50x20^:1 a-si/sin/a-si^:1 achieved^:1 alpha^:1 applications^:1 assessment^:1 atom^:1 automatons^:1 block^:1 circuits^:1 complementary^:1 crossbars^:1 csb^:1 delay^:1 detection^:1 dynamically^:1 embedded^:1 enhancement^:1

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論文誌

[1] H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, and M. Hashimoto, "Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars," IEEE Transactions on VLSI Systems, volume 26, number 12, pages 2723--2736, December 2018. [pdf]

[2] T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices," IEICE Trans. on Information and Systems, volume E96-D, number 8, pages 1624--1631, August 2013. [191.pdf]

[3] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "PVT-induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices," IEICE Electronics Express (ELEX), volume 10, number 5, April 2013. [184.pdf]

国際会議

[1] N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch for a Highly-Dense Reconfigurable Logic," Technical Digest of IEEE International Electron Devices Meeting (IEDM), December 2016. [231.PDF]

[2] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2016. [pdf]

[3] T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2012. [170.pdf]

[4] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 189--194, September 2011. [162.pdf]

[5] D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "MTTF Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability," IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.

著書

[1] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, and M. Tada, "Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.