Academic Journal
|
H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E94-A(12)
|
2545--2553
|
December 2011
|
| 166.pdf
|
Academic Journal
|
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, M. Hashimoto
|
Gate Delay Estimation in STA under Dynamic Power Supply Noise
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E93-A(12)
|
2447--2455
|
December 2010
|
| 151.pdf
|
Academic Journal
|
Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue
|
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 29(2)
|
250--260
|
February 2010
|
| 134.pdf
|
Academic Journal
|
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye
|
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement
|
IEEE Transactions on Circuits and Systems II
| 54(10)
|
868--872
|
October 2007
|
| 94.pdf
|
Academic Journal
|
M. Hashimoto, H. Onodera, K. Tamaru
|
A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E82-A(1)
|
159-166
|
January 1999
|
| 19.pdf
|
International Conference
|
M. Hashimoto, Y. Nakazawa, R. Doi, J. Yu
|
Interconnect Delay Analysis for RRAM Crossbar Based FPGA (Invited)
|
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
|
|
|
July 2018
|
| pdf
|
International Conference
|
L. Zhang, B. Li, M. Hashimoto. U. Schlichtmann
|
VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units
|
Proceedings of Design Automation Conference (DAC)
|
|
|
June 2018
|
| pdf
|
International Conference
|
T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture
|
Proceedings of International Conference on Field Programmable Logic and Applications (FPL)
|
|
|
August 2012
|
| 170.pdf
|
International Conference
|
Y. Takai, Y. Ogasahara, M. Hashimoto, T. Onoye
|
Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to SSO
|
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)
|
|
19--20
|
May 2010
|
| 139.pdf
|
International Conference
|
H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Comparative Study on Delay Degrading Estimation Due to NBTI with Circuit/Instance/Transistor-Level Stress Probability Consideration
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
646--651
|
March 2010
|
| 137.pdf
|
International Conference
|
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, M. Hashimoto
|
Gate Delay Estimation in STA under Dynamic Power Supply Noise
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
775 -- 780
|
January 2010
|
| 132.pdf
|
Domestic Conference
|
, R. Doi, M. Hashimoto
|
Rc Extraction-Free Wiring Delay Analysis Focusing on Number of On-State Switches for Via-Switch Fpga
|
情報処理学会DAシンポジウム
|
|
|
August 2019
|
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