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論文誌

[1] A. Lopez, Y. Okoshi, M. Hashimoto, M. Motomura, and J. Yu, "Recurrent Residual Networks Contain Stronger Lottery Tickets," IEEE Access, volume 11, 16588 - 16604, February 2023. [pdf]

[2] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation," Japanese Journal of Applied Physics, volume 61, number SM0804, October 2022. [pdf]

[3] R. Doi, J. Yu, and M. Hashimoto, "Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-Switch Crossbar Based FPGA," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 39, number 10, pages 2572--2587, October 2020. [pdf]

[4] T. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, "Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training," Integration, the VLSI Journal, volume 74, pages 19--31, September 2020. [pdf]

[5] H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, and M. Hashimoto, "Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars," IEEE Transactions on VLSI Systems, volume 26, number 12, pages 2723--2736, December 2018. [pdf]

[6] K. Mitsunari, J. Yu, T. Onoye, and M. Hashimoto, "Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E101-A, number 9, pages 1298--1307, September 2018. [pdf]

国際会議

[1] M. Tanaka, J. Yu, M. Nakagawa, N. Tate, and M. Hashimoto, "Investigating Small Device Implementation of FRET-Based Optical Reservoir Computing," Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2022. [pdf]

[2] A. Lopez, M. Hashimoto, M. Motomura, and J. Yu, "Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks," Proceedings of British Machine Vision Conference (BMVC), November 2021. [pdf]

[3] T. Imagawa, J. Yu, M. Hashimoto, and H. Ochi, "MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA," Proceedings of Design, Automation and Test in Europe Conference (DATE), February 2021. [pdf]

[4] A. Lopez, J. Yu, and M. Hashimoto, "Low-Cost Reservoir Computing Using Cellular Automata and Random Forests," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), October 2020. [pdf]

[5] K. Onishi, J. Yu, and M. Hashimoto, "Memory Efficient Training Using Lookup-Table-Based Quantization for Neural Network," Proceedings of International Conference on Artificial Intelligence Circuits and Systems (AICAS), August 2020. [pdf]

[6] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), pages 502--503, February 2020. [pdf]

[7] T. Tanio, J. Yu, and M. Hashimoto, "Training Data Reduction Using Support Vectors for Neural Networks," Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC), November 2019. [pdf]

[8] S. Fukui, J. Yu, and M. Hashimoto, "Distilling Knowledge for Non-Neural Networks," Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC), November 2019. [pdf]

[9] S. Sombatsiri, J. Yu, M. Hashimoto, and Y. Takeuchi, "A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2019.

[10] T.-Y. Cheng, J. Yu, and M. Hashimoto, "Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier," Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), July 2019. [pdf]

[11] R. Doi, J. Yu, and M. Hashimoto, "Sneak Path Free Reconfiguration of Via-Switch Crossbars Based FPGA," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2018. [pdf]

[12] K. Mitsunari, J. Yu, and M. Hashimoto, "Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 55-58, November 2018. [pdf]

[13] K. Itoh, J. Yu, and M. Hashimoto, "Adapting Soft Cascade to Mac Operations of Convolutional Neural Networks," Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC), August 2018.

[14] M. Hashimoto, Y. Nakazawa, R. Doi, and J. Yu, "Interconnect Delay Analysis for RRAM Crossbar Based FPGA (Invited)," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018. [pdf]