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論文誌

[1] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E105-A, number 3, pages 497--508, March 2022. [pdf]

[2] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , and M. Hashimoto, "Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 105-A, number 3, pages 509--517, March 2022. [pdf]

[3] T. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, "Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training," Integration, the VLSI Journal, volume 74, pages 19--31, September 2020. [pdf]

国際会議

[1] T. Cheng and M. Hashimoto, "Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2021. [pdf]

[2] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design," Proceedings of Design, Automation and Test in Europe Conference (DATE), February 2021. [pdf]

[3] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 284 -- 290, January 2021. [pdf]

[4] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling," International Workshop on Logic and Synthesis (IWLS), July 2020.

[5] T.-Y. Cheng, J. Yu, and M. Hashimoto, "Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier," Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), July 2019. [pdf]

研究会・全国大会等

[1] T.-Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," 電子情報通信学会 VLSI設計技術研究会, March 2021.