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Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , and M. Hashimoto, "Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, 105-A(3), pp. 509--517, March 2022. | |
ID | 576 |
分類 | 論文誌 |
タグ | bit-width circuit critical design isolation low-power methodology over-scalable path scaling voltage |
表題 (title) |
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling |
表題 (英文) |
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著者名 (author) |
Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama,,M. Hashimoto |
英文著者名 (author) |
,M. Hashimoto |
キー (key) |
,M. Hashimoto |
定期刊行物名 (journal) |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences |
定期刊行物名 (英文) |
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巻数 (volume) |
105-A |
号数 (number) |
3 |
ページ範囲 (pages) |
509--517 |
刊行月 (month) |
3 |
出版年 (year) |
2022 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id576, title = {Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling}, author = {Y. Masuda and J. Nagayama and T. Cheng and T. Ishihara and Y. Momiyama and and M. Hashimoto}, journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences}, volume = {105-A}, number = {3}, pages = {509--517}, month = {3}, year = {2022}, } |