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論文誌
[1] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , and M. Hashimoto, "Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 105-A, number 3, pages 509--517, March 2022. [pdf]
[2] R. Doi, J. Yu, and M. Hashimoto, "Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-Switch Crossbar Based FPGA," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 39, number 10, pages 2572--2587, October 2020. [pdf]
国際会議
[1] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design," Proceedings of Design, Automation and Test in Europe Conference (DATE), February 2021. [pdf]
[2] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling," International Workshop on Logic and Synthesis (IWLS), July 2020.
[3] R. Doi, J. Yu, and M. Hashimoto, "Sneak Path Free Reconfiguration of Via-Switch Crossbars Based FPGA," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2018. [pdf]
[4] R. Doi and M. Hashimoto, "SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018. [pdf]
[5] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Return Path Selection for Loop RL Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1078-1081, January 2005. [33.pdf]