この検索内の頻出タグ: methodology^:8 design^:6 mttf-aware^:3 voltage^:3 adaptively^:2 circuit^:2 error^:2 estimation^:2 invited^:2 irradiation^:2 neutron^:2 scaling^:2 ser^:2 simulation^:2 terrestrial^:2 adaptive^:1 applicable^:1 asic^:1 bit-width^:1 circuits^:1 conventional^:1 coupled^:1 critical^:1 distribution^:1 diverse^:1 flip-flop^:1 generation^:1 isolation^:1 library^:1 low-power^:1

8 件の該当がありました． : このページのURL : HTML

論文誌

[1] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology Based on Simulation Coupled with One-Time Neutron Irradiation Testing," IEEE Transactions on Nuclear Science, volume 70, number 8, 1652 -- 1657, August 2023. [pdf]

[2] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , and M. Hashimoto, "Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 105-A, number 3, pages 509--517, March 2022. [pdf]

[3] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 102-A, number 7, pages 867--877, July 2019. [pdf]

国際会議

[1] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology with Simulation and Single-Source Irradiation Applicable to Diverse Neutron Sources," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022.

[2] M. Hashimoto and J. Chen, "Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2021. [pdf]

[3] M. Hashimoto and Y. Masuda, "MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2018. [pdf]

[4] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018. [pdf]

[5] H. Onodera, M. Hashimoto, and T. Hashimoto, "ASIC Design Methodology with On-Demand Library Generation," In Proceedings of Symposium on VLSI Circuits, pages 57-60, June 2001. [59.pdf]