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Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, 102-A(7), pp. 867--877, July 2019. | |
ID | 507 |
分類 | 論文誌 |
タグ | adaptively circuit design error flip-flop methodology mttf-aware predictive scaled timing voltage |
表題 (title) |
MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop |
表題 (英文) |
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著者名 (author) |
Y. Masuda,M. Hashimoto |
英文著者名 (author) |
Y. Masuda,M. Hashimoto |
キー (key) |
Y. Masuda,M. Hashimoto |
定期刊行物名 (journal) |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences |
定期刊行物名 (英文) |
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巻数 (volume) |
102-A |
号数 (number) |
7 |
ページ範囲 (pages) |
867--877 |
刊行月 (month) |
7 |
出版年 (year) |
2019 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id507, title = {{MTTF-aware} Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop}, author = {Y. Masuda and M. Hashimoto}, journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences}, volume = {102-A}, number = {7}, pages = {867--877}, month = {7}, year = {2019}, } |