Academic Journal
|
, Y. Masuda, , , J. Chen, M. Hashimoto
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Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization
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IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E105-A(3)
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497--508
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March 2022
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| pdf
|
Academic Journal
|
, M. Hashimoto
|
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 105-A(3)
|
509--517
|
March 2022
|
| pdf
|
Academic Journal
|
J. Chen, M. Hashimoto
|
A Frequency-Dependent Target Impedance Method Fulfilling Voltage Drop Constraints in Multiple Frequency Ranges
|
IEEE Transactions on Components, Packaging and Manufacturing Technology
| 10(11)
|
1769 -- 1781
|
November 2020
|
| pdf
|
Academic Journal
|
Y. Masuda, M. Hashimoto
|
MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 102-A(7)
|
867--877
|
July 2019
|
| pdf
|
Academic Journal
|
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
|
Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment
|
IEEE Transactions on Nuclear Science
| 60(6)
|
4232--4237
|
December 2013
|
| 198.pdf
|
Academic Journal
|
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
|
Timing Analysis Considering Temporal Supply Voltage Fluctuation
|
IEICE Trans. on Information and Systems
| E91-D(3)
|
655--660
|
March 2008
|
| 101.pdf
|
Academic Journal
|
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye
|
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement
|
IEEE Transactions on Circuits and Systems II
| 54(10)
|
868--872
|
October 2007
|
| 94.pdf
|
International Conference
|
, T. Kato, M. Hashimoto
|
An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs
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Proceedings of International Symposium on Reliability Physics (IRPS)
|
|
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April 2024
|
| pdf
|
International Conference
|
, M. Hashimoto
|
Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling
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Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
|
|
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May 2021
|
| pdf
|
International Conference
|
Y. Masuda, , , , , M. Hashimoto
|
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design
|
Proceedings of Design, Automation and Test in Europe Conference (DATE)
|
|
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February 2021
|
| pdf
|
International Conference
|
J. Chen, M. Hashimoto
|
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction
|
Proceedings of International Test Conference (ITC)
|
|
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November 2020
|
| pdf
|
International Conference
|
Y. Masuda, , , , , M. Hashimoto
|
Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling
|
International Workshop on Logic and Synthesis (IWLS)
|
|
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July 2020
|
|
|
International Conference
|
J. Chen, M. Hashimoto
|
A Frequency-Dependent Target Impedance Method Fulfilling both Average and Dynamic Voltage Drop Constraints
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Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)
|
|
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June 2019
|
| pdf
|
International Conference
|
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Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors
|
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
|
|
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November 2018
|
| pdf
|
International Conference
|
J. Chen, T. Kanamoto, H. Kando, M. Hashimoto
|
An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency
|
Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)
|
|
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May 2018
|
| pdf
|
International Conference
|
M. Hashimoto, Y. Masuda
|
MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited)
|
Proceedings of China Semiconductor Technology International Conference (CSTIC)
|
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March 2018
|
| pdf
|
International Conference
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S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake
|
Momentum and Supply Voltage Dependencies of SEUs Induced by Low-Energy Negative and Positive Muons in 65-nm UTBB-SOI SRAMs
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Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
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October 2017
|
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International Conference
|
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
|
Soft-Error in SRAM at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
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July 2013
|
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