Academic Journal
|
J. Chen, H. Kando, T. Kanamoto, , M. Hashimoto
|
A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions
|
IEEE Transactions on Components, Packaging and Manufacturing Technology
| 9(9)
|
1669--1679
|
September 2019
|
| pdf
|
Academic Journal
|
T. Enami, K. Shinkai, S. Ninomiya, S. Abe, M. Hashimoto
|
Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E93-A(12)
|
2399--2408
|
December 2010
|
| 148.pdf
|
Academic Journal
|
T. Enami, S. Ninomiya, M. Hashimoto
|
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 28(4)
|
541 - 553
|
April 2009
|
| 118.pdf
|
Academic Journal
|
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
|
Timing Analysis Considering Temporal Supply Voltage Fluctuation
|
IEICE Trans. on Information and Systems
| E91-D(3)
|
655--660
|
March 2008
|
| 101.pdf
|
International Conference
|
J. Chen, T. Kanamoto, H. Kando, M. Hashimoto
|
An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency
|
Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)
|
|
|
May 2018
|
| pdf
|
International Conference
|
K.-W. Lin, M. Hashimoto, Y.-L. Li
|
Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles Considering Traffic Uncertainties
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
|
March 2018
|
| pdf
|
