|
Author (author) |
Title (title) |
Journal/Conference |
Volume / Number |
Pages (pages) |
Published date |
Impact factor / Acceptance |
File |
Academic Journal
|
T. Enami, K. Shinkai, S. Ninomiya, S. Abe, M. Hashimoto
|
Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E93-A(12)
|
2399--2408
|
December 2010
|
| 148.pdf
|
Academic Journal
|
T. Miyazaki, M. Hashimoto, H. Onodera
|
A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL
|
IEICE Trans. on Electronics
| E88-C(3)
|
437-444
|
March 2005
|
| 89.pdf
|
International Conference
|
J. Chen, T. Kanamoto, H. Kando, M. Hashimoto
|
An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency
|
Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)
|
|
|
May 2018
|
| pdf
|
International Conference
|
T. Miyazaki, M. Hashimoto, H. Onodera
|
A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL
|
IEEJ International Analog VLSI Workshop
|
|
45-50
|
October 2004
|
|
|
International Conference
|
T. Miyazaki, M. Hashimoto, H. Onodera
|
A Performance Comparison of PLLs for Clock Generation Using Ring Oscillator VCO and LC Oscillator in a Digital CMOS Process
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
545-546
|
January 2004
|
| 36.pdf
|