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論文誌

[1] X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, "Via-Switch FPGA: 65nm CMOS Implementation and Evaluation," IEEE Journal of Solid-State Circuits, volume 57, number 7, pages 2250-2262, July 2022. [pdf]

[2] I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, "A 0.8-V 110-nA CMOS Current Reference Circuit Using Subthreshold Operation," IEICE Electronics Express (ELEX), volume 10, number 4, March 2013. [182.pdf]

[3] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 2, pages 250--260, February 2010. [134.pdf]

[4] M. Hashimoto, H. Onodera, and K. Tamaru, "A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E82-A, number 1, pages 159-166, January 1999. [19.pdf]

国際会議

[1] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), pages 502--503, February 2020. [pdf]

[2] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, S. Takeshita, and Y. Miyake, "Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs," Proceedings of International Reliability Physics Symposium (IRPS), April 2019. [pdf]

[3] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 nm Bulk CMOS," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]

[4] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.

[5] S. Uemura, T. Miyazaki, M. Hashimoto, and H. Onodera, "Estimation of Maximum Oscillation Frequency for CMOS LCVCOs," In Proceedings of IEEJ International Analog VLSI Workshop, October 2005.

[6] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um CMOS Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), D9-D10, January 2005. [35.pdf]

[7] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Optimization of CMOS Current Mode Logic Dividers," In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pages 434-435, August 2004. [55.pdf]

[8] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Comparison of PLLs for Clock Generation Using Ring Oscillator VCO and LC Oscillator in a Digital CMOS Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 545-546, January 2004. [36.pdf]