Academic Journal
|
, , , , , M. Hashimoto
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A 292.2-To-321.4 Ghz Synchronized Source Generator with ‒58.7 Dbc Spurious Tone and 128.4 Fsrms Integrated Jitter in 22 Nm Cmos Technology
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IEEE Transactions on Microwave Theory and Techniques
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(accepted, to appear)
|
|
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Academic Journal
|
, , , , , , M. Hashimoto
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Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS
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IEEE Transactions on Circuits and Systems II
|
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(accepted, to appear)
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Academic Journal
|
, N. Banno, M. Miyamura, , K. Okamoto, , N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada
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Via-Switch FPGA: 65nm CMOS Implementation and Evaluation
|
IEEE Journal of Solid-State Circuits
| 57(7)
|
2250-2262
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July 2022
|
| pdf
|
Academic Journal
|
I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, T. Onoye
|
A 0.8-V 110-nA CMOS Current Reference Circuit Using Subthreshold Operation
|
IEICE Electronics Express (ELEX)
| 10(4)
|
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March 2013
|
| 182.pdf
|
Academic Journal
|
Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue
|
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 29(2)
|
250--260
|
February 2010
|
| 134.pdf
|
Academic Journal
|
M. Hashimoto, H. Onodera, K. Tamaru
|
A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E82-A(1)
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159-166
|
January 1999
|
| 19.pdf
|
International Conference
|
M. Hashimoto, , N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, , H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi
|
Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications
|
Technical Digest of International Solid-State Circuits Conference (ISSCC)
|
|
502--503
|
February 2020
|
| pdf
|
International Conference
|
W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, , Y. Miyake
|
Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
|
April 2019
|
| pdf
|
International Conference
|
T. Uemura, S. Okano, T. Kato, H. Matsuyama, M. Hashimoto
|
Soft Error Immune Latch Design for 20 nm Bulk CMOS
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
|
April 2015
|
| 217.pdf
|
International Conference
|
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
|
Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
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July 2013
|
|
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International Conference
|
S. Uemura, T. Miyazaki, M. Hashimoto, H. Onodera
|
Estimation of Maximum Oscillation Frequency for CMOS LCVCOs
|
Proceedings of IEEJ International Analog VLSI Workshop
|
|
|
October 2005
|
|
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International Conference
|
A. Shinmyo, M. Hashimoto, H. Onodera
|
Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um CMOS Process
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
D9-D10
|
January 2005
|
| 35.pdf
|
International Conference
|
A. Shinmyo, M. Hashimoto, H. Onodera
|
Design and Optimization of CMOS Current Mode Logic Dividers
|
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
|
|
434-435
|
August 2004
|
| 55.pdf
|
International Conference
|
T. Miyazaki, M. Hashimoto, H. Onodera
|
A Performance Comparison of PLLs for Clock Generation Using Ring Oscillator VCO and LC Oscillator in a Digital CMOS Process
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
545-546
|
January 2004
|
| 36.pdf
|
