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M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), pp. 502--503, February 2020. | |
ID | 529 |
分類 | 国際会議 |
タグ | 65-nm ai applications architecture cmos extension first fpga implementation via-switch |
表題 (title) |
Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications |
表題 (英文) |
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著者名 (author) |
M. Hashimoto,X. Bai,N. Banno,M. Tada,T. Sakamoto,J. Yu,R. Doi,Y. Araki,H. Onodera,T. Imagawa,H. Ochi,K. Wakabayashi,Y. Mitsuyama,T. Sugibayashi |
英文著者名 (author) |
M. Hashimoto,,N. Banno,M. Tada,T. Sakamoto,J. Yu,R. Doi,,H. Onodera,T. Imagawa,H. Ochi,K. Wakabayashi,Y. Mitsuyama,T. Sugibayashi |
キー (key) |
M. Hashimoto,,N. Banno,M. Tada,T. Sakamoto,J. Yu,R. Doi,,H. Onodera,T. Imagawa,H. Ochi,K. Wakabayashi,Y. Mitsuyama,T. Sugibayashi |
定期刊行物名 (journal) |
Technical Digest of International Solid-State Circuits Conference (ISSCC) |
定期刊行物名 (英文) |
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巻数 (volume) |
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号数 (number) |
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ページ範囲 (pages) |
502--503 |
刊行月 (month) |
2 |
出版年 (year) |
2020 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id529, title = {Via-Switch {FPGA}: 65nm {CMOS} Implementation and Architecture Extension for {AI} Applications}, author = {M. Hashimoto and X. Bai and N. Banno and M. Tada and T. Sakamoto and J. Yu and R. Doi and Y. Araki and H. Onodera and T. Imagawa and H. Ochi and K. Wakabayashi and Y. Mitsuyama and T. Sugibayashi}, journal = {Technical Digest of International Solid-State Circuits Conference (ISSCC)}, pages = {502--503}, month = {2}, year = {2020}, } |