Search: 簡易 | 詳細 || Language: 英語 | 日本語 || ログイン |

14 件の該当がありました. : このページのURL : HTML


論文誌
[1] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Exploring Well-Configurations for Minimizing Single Event Latchup," IEEE Transactions on Nuclear Science, volume 61, number 6, pages 3282--3289, December 2014. [211.pdf]
[2] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4362--4367, December 2013. [197.pdf]
[3] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4232--4237, December 2013. [198.pdf]
[4] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, volume 59, number 6, pages 2791--2795, December 2012. [175.pdf]
国際会議
[1] T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, "Impact of Package on Neutron Induced Single Event Upset in 20 nm SRAM," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015. [215.pdf]
[2] T. Uemura and M. Hashimoto, "Investigation of Single Event Upset and Total Ionizing Dose in FeRAM for Medical Electronic Tag," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015. [216.pdf]
[3] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 nm Bulk CMOS," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]
[4] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Optimizing Well-Configuration for Minimizing Single Event Latchup," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[5] T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, "Preventing Single Event Latchup with Deep P-Well on P-Substrate," Proceedings of International Reliability Physics Symposium (IRPS), June 2014. [203.pdf]
[6] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[7] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in SRAM at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[8] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[9] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2012.
[10] S. Uemura, T. Miyazaki, M. Hashimoto, and H. Onodera, "Estimation of Maximum Oscillation Frequency for CMOS LCVCOs," In Proceedings of IEEJ International Analog VLSI Workshop, October 2005.