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26 publications are found. : URL for this page. : HTML


Author (author) Title (title) Journal/Conference Volume / Number Pages (pages) Published date Impact factor / Acceptance File
Academic Journal
, , , , , , , Y. Watanabe, S. Abe, W. Liao, M. Tampo, , , Y. Miyake, M. Hashimoto
Muon-Induced SEU Analysis and Simulation for Different Cell Types in 12-nm FinFET SRAMs, and 28-nm Planar SRAMs and Register Files
IEEE Transactions on Nuclear Science
72(8)
2751 - 2762
August 2025

pdf
Academic Journal
J. Chen, H. Kando, T. Kanamoto, , M. Hashimoto
A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions
IEEE Transactions on Components, Packaging and Manufacturing Technology
9(9)
1669--1679
September 2019

pdf
Academic Journal
T. Nakayama, M. Hashimoto
Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
102-A(7)
914--917
July 2019

pdf
Academic Journal
W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe
Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM
IEEE Transactions on Nuclear Science
66(7)
1390 -- 1397
July 2019

pdf
Academic Journal
H. Fuketa, R. Harada, M. Hashimoto, T. Onoye
Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM
IEEE Transactions on Device and Materials Reliability
14(1)
463 -- 470
March 2014

185.pdf
Academic Journal
T. Enami, K. Shinkai, S. Ninomiya, S. Abe, M. Hashimoto
Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E93-A(12)
2399--2408
December 2010

148.pdf
Academic Journal
Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
29(2)
250--260
February 2010

134.pdf
Academic Journal
T. Enami, S. Ninomiya, M. Hashimoto
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
28(4)
541 - 553
April 2009

118.pdf
Academic Journal
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
Timing Analysis Considering Temporal Supply Voltage Fluctuation
IEICE Trans. on Information and Systems
E91-D(3)
655--660
March 2008

101.pdf
Academic Journal
T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
E88-A(12)
3382-3389
December 2005

9.pdf
Academic Journal
M. Hashimoto, Y. Yamada, H. Onodera
Equivalent Waveform Propagation for Static Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
23(4)
498-508
April 2004

20.pdf
International Conference

Window Function-Less DFT with Reduced Noise and Latency for Real-Time Music Analysis
Proceedings of European Signal Processing Conference (EUSIPCO)


(accepted, to appear)


International Conference
, , , , , , , M. Hashimoto
Tenpura: a General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-Fast Reliability Analysis
Proceedings of International Conference on Computer-Aided Design (ICCAD)


(accepted, to appear)


International Conference
and
Gundam: a Generalized Unified Design and Analysis Model for Matrix Multiplication on Edge
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)


(accepted, to appear)


International Conference

Genshin: a Generalized Framework with Software-Hardware Co-Design and Pruned Fault Injection for Reliability Analysis
Proceedings of International Test Conference (ITC)


September 2025

pdf
International Conference

Muon-Induced SEU Analysis and Simulation for Different Cell Types in 12-nm FinFET SRAMs
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)


September 2024


International Conference

Processor SER Estimation with ACE Bit Analysis
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)


September 2021


International Conference
Y. Zhang, , , , , M. Hashimoto
Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)


October 2020


International Conference
W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe
Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)


September 2018


International Conference
M. Hashimoto, Y. Nakazawa, R. Doi, J. Yu
Interconnect Delay Analysis for RRAM Crossbar Based FPGA (Invited)
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI)


July 2018

pdf
International Conference
J. Chen, T. Kanamoto, H. Kando, M. Hashimoto
An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency
Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)


May 2018

pdf
International Conference
T. Nakayama, M. Hashimoto
Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature
Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT)


April 2018

pdf
International Conference
S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, Y. Watanabe
Neutron-Induced SEU and MCU Rate Characterization and Analysis of SOTB and Bulk SRAMs at 0.3V Operation
IEEE Nuclear and Space Radiation Effects Conference (NSREC)


July 2015


International Conference
T. Sato, N. Ono, J. Ichimiya, K. Hachiya, M. Hashimoto
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)

1074-1077
January 2005

34.pdf
International Conference
A. Muramatsu, M. Hashimoto, H. Onodera
LSI Power Network Analysis with On-Chip Wire Inductance
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)

55-60
October 2004


Domestic Conference
, R. Doi, M. Hashimoto
Rc Extraction-Free Wiring Delay Analysis Focusing on Number of On-State Switches for Via-Switch Fpga
情報処理学会DAシンポジウム


August 2019