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20 件の該当がありました． : このページのURL : HTML

論文誌

[1] J. Chen, H. Kando, T. Kanamoto, C. Zhuo, and M. Hashimoto, "A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions," IEEE Transactions on Components, Packaging and Manufacturing Technology, volume 9, number 9, pages 1669--1679, September 2019. [pdf]

[2] T. Nakayama and M. Hashimoto, "Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 102-A, number 7, pages 914--917, July 2019. [pdf]

[3] W. Liao, M. Hashimoto, S. Manabe, S. Abe, and Y. Watanabe, "Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM," IEEE Transactions on Nuclear Science, volume 66, number 7, 1390 -- 1397, July 2019. [pdf]

[4] H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM," IEEE Transactions on Device and Materials Reliability, volume 14, number 1, 463 -- 470, March 2014. [185.pdf]

[5] T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2399--2408, December 2010. [148.pdf]

[6] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 2, pages 250--260, February 2010. [134.pdf]

[7] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 4, 541 - 553, April 2009. [118.pdf]

[8] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," IEICE Trans. on Information and Systems, volume E91-D, number 3, pages 655--660, March 2008. [101.pdf]

[9] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3382-3389, December 2005. [9.pdf]

[10] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 23, number 4, pages 498-508, April 2004. [20.pdf]

国際会議

[1] T. Hsu, D. Yang, W. Liao, M. Itoh, M. Hashimoto, , and J. Liou, "Processor SER Estimation with ACE Bit Analysis," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2021.

[2] Y. Zhang, K. Ito, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2020.

[3] W. Liao, M. Hashimoto, S. Manabe, S. Abe, and Y. Watanabe, "Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.

[4] M. Hashimoto, Y. Nakazawa, R. Doi, and J. Yu, "Interconnect Delay Analysis for RRAM Crossbar Based FPGA (Invited)," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018. [pdf]

[5] J. Chen, T. Kanamoto, H. Kando, and M. Hashimoto, "An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency," Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), May 2018. [pdf]

[6] T. Nakayama and M. Hashimoto, "Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature," Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2018. [pdf]

[7] S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, "Neutron-Induced SEU and MCU Rate Characterization and Analysis of SOTB and Bulk SRAMs at 0.3V Operation," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.

[8] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1074-1077, January 2005. [34.pdf]

[9] A. Muramatsu, M. Hashimoto, and H. Onodera, "LSI Power Network Analysis with On-Chip Wire Inductance," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 55-60, October 2004.

国内会議(査読付き)

[1] Y. Sun, R. Doi, and M. Hashimoto, "Rc Extraction-Free Wiring Delay Analysis Focusing on Number of On-State Switches for Via-Switch Fpga," 情報処理学会DAシンポジウム, August 2019.