: J. Chen, T. Kanamoto, H. Kando, and M. Hashimoto, An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency, May 2018.
Detail of a work
| Tweet | |
| J. Chen, T. Kanamoto, H. Kando, and M. Hashimoto, "An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency," Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), May 2018. | |
| ID | 475 |
| 分類 | 国際会議 |
| タグ | analysis clock considering current interdependency latency load model off-chip on-chip pdn profile supply voltage |
| 表題 (title) |
An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency |
| 表題 (英文) |
|
| 著者名 (author) |
J. Chen,T. Kanamoto,H. Kando,M. Hashimoto |
| 英文著者名 (author) |
J. Chen,T. Kanamoto,H. Kando,M. Hashimoto |
| キー (key) |
J. Chen,T. Kanamoto,H. Kando,M. Hashimoto |
| 定期刊行物名 (journal) |
Proceedings of IEEE Workshop on Signal and Power Integrity (SPI) |
| 定期刊行物名 (英文) |
|
| 巻数 (volume) |
|
| 号数 (number) |
|
| ページ範囲 (pages) |
|
| 刊行月 (month) |
5 |
| 出版年 (year) |
2018 |
| Impact Factor (JCR) |
|
| URL |
|
| 付加情報 (note) |
|
| 注釈 (annote) |
|
| 内容梗概 (abstract) |
|
| 論文電子ファイル | pdf (application/pdf) [一般閲覧可] |
| BiBTeXエントリ |
@article{id475,
title = {An On-Chip Load Model for Off-Chip {PDN} Analysis Considering Interdependency Between Supply Voltage, Current Profile and Clock Latency},
author = {J. Chen and T. Kanamoto and H. Kando and M. Hashimoto},
journal = {Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)},
month = {5},
year = {2018},
}
|