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論文誌

[1] J. Chen, H. Kando, T. Kanamoto, C. Zhuo, and M. Hashimoto, "A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions," IEEE Transactions on Components, Packaging and Manufacturing Technology, volume 9, number 9, pages 1669--1679, September 2019. [pdf]

国際会議

[1] J. Chen, T. Kanamoto, H. Kando, and M. Hashimoto, "An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency," Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), May 2018. [pdf]