この検索内の頻出タグ: atom^:3 complementary^:3 crossbar^:3 fpga^:3 nuclear^:3 selected^:3 switch^:3 two-varistors^:3 via-switch^:3 a-si/sin/a-si^:2 analysis^:2 capture^:2 design^:2 flattening^:2 gradient^:2 muon^:2 nonvolatile^:2 on-chip^:2 reaction^:2 soc^:2 temperature^:2 thermal^:2 28^:1 29^:1 2v-1cas^:1 2v-1cas;^:1 30si^:1 50x20^:1 65-nm^:1 accuracy^:1

17 件の該当がありました． : このページのURL : HTML

論文誌

[1] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation," Japanese Journal of Applied Physics, volume 61, number SM0804, October 2022. [pdf]

[2] N. Banno, K. Okamoto, N. Iguchi, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, "Low-Power Crossbar Switch with Two-Varistors Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA," IEEE Transactions on Electron Devices, volume 66, number 8, pages 3331--3336, August 2019. [pdf]

[3] T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, "Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 92-A, number 4, pages 990--997, April 2009. [119.pdf]

[4] H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, and M. Hashimoto, "Proposal of Metrics for SSTA Accuracy Evaluation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 4, pages 808--814, April 2007. [81.pdf]

[5] T. Sato, J. Ichimiya, N. Ono, and M. Hashimoto, "On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3491-3499, December 2006. [4.pdf]

[6] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3382-3389, December 2005. [9.pdf]

国際会議

[1] R. Mizuno, M. Niikura, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki, A. Hillier, T. Kawata, K. Kitafuji, Y. Yamaguchi, D. Tomono, and F. Minato, "In-Beam Activation Measurement of Muon Nuclear Capture Reaction on Si Isotopes," The workshop on frontier nuclear studies with gamma-ray spectrometer arrays (gamma24), March 2024.

[2] R. Mizuno, M. Niikura, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki, A. Hillier, T. Kawata, K. Kitafuji, Y. Yamaguchi, D. Tomono, and F. Minato, "Muon Nuclear Capture Reaction on 28,29,30si," 2023 Fall meeting of APS DNP and JPS, November 2023.

[3] M. Niikura, R. Mizuno, S. Manabe, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, A. Hillier, N. Kawamura, Y. Kawashima, S. Kawase, T. Kawata, K. Kitafuji, F. Minato, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, M. Tampo, D. Tomono, I. Umegaki, Y. Yamaguchi, and Y. Watanabe, "Nuclear Physics for Muon-Induced Soft Error," Workshop for Computational Technique for Negative Muon Spectroscopy and Elemental Analysis, August 2023.

[4] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), pages 502--503, February 2020. [pdf]

[5] N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch for a Highly-Dense Reconfigurable Logic," Technical Digest of IEEE International Electron Devices Meeting (IEDM), December 2016. [231.PDF]

[6] H. Hihara, A. Iwasaki, N. Tamagawa, M. Kuribayashi, M. Hashimoto, Y. Mitsuyama, H. Ochi, H. Onodera, H. Kanbara, K. Wakabayashi, and T. Sugibayashi, "Novel Processor Architecture for Onboard Infrared Sensors (Invited)," Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV, volume 9973, August 2016.

[7] N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-Outs," Technical Digest of IEEE International Electron Devices Meeting (IEDM), pages 32--35, December 2015. [225.PDF]

[8] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1074-1077, January 2005. [34.pdf]

国内会議(査読付き)

[1] 小林宏行, 小野信任, 佐藤高史, 岩井二郎, 橋本昌宜, "統計的STAの有効性の検証手法," 第19回 回路とシステム(軽井沢)ワークショップ, pages 553-558, 2006年4月. [74.pdf]

[2] 佐藤高史, 市宮淳次, 小野信任, 蜂屋孝太郎, 橋本昌宜, "フロアプランにおけるオンチップ熱ばらつきの解析と対策," 情報処理学会DAシンポジウム, pages 133-138, 2004年7月.

研究会・全国大会等

[1] R. Mizuno, M. Niikura, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki, A. Hillier, T. Kawata, K. Kitafuji, and D. Tomono, "ミューオン原子核捕獲反応による生成核分岐比の測定," 第12回停止・低速RIビームを用いた核分光研究会 (12th SSRI), September 2023.