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19 件の該当がありました． : このページのURL : HTML

論文誌

[1] H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM," IEEE Transactions on Device and Materials Reliability, volume 14, number 1, 463 -- 470, March 2014. [185.pdf]

[2] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, volume 59, number 6, pages 2791--2795, December 2012. [175.pdf]

[3] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 20, number 2, pages 333--343, February 2012. [155.pdf]

[4] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, volume 58, number 4, pages 2097--2102, August 2011. [159.pdf]

[5] H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, "An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion," IEEE Transactions on Circuits and Systems II, volume 58, number 5, pages 299--303, May 2011. [158.pdf]

[6] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 18, number 7, pages 1118--1129, July 2010. [130.pdf]

[7] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3094--3102, December 2009. [128.pdf]

[8] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," IEICE Trans. on Electronics, volume E92-C, number 2, pages 281--285, February 2009. [117.pdf]

国際会議

[1] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2012.

[2] M. Hashimoto and H. Fuketa, " Adaptive Performance Compensation with On-Chip Variation Monitoring (Invited)," Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011. [160.pdf]

[3] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," Proceedings of International Reliability Physics Symposium (IRPS), pages 213--217, May 2010. [140.PDF]

[4] D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, "A 16-Bit RISC Processor with 4.18pJ/cycle at 0.5V Operation," Proceedings of IEEE COOL Chips, page 190, April 2010. [145.pdf]

[5] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 361 -- 362, January 2010. [131.pdf]

[6] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 215--218, September 2009. [127.pdf]

[7] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 266-271, January 2009. [116.pdf]

[8] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits," Proceedings of Workshop on Test Structure Design for Variability Characterization, November 2008.

[9] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 3--8, August 2008. [106.pdf]

[10] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Experimental Study on Body-Biasing Layout Style -- Negligible Area Overhead Enables Sufficient Speed Controllability --," Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI), pages 387--390, May 2008. [104.pdf]

[11] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 233-237, October 2007.