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T. Nakayama and M. Hashimoto, "Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, 102-A(7), pp. 914--917, July 2019.
ID 497
分類 論文誌
タグ analysis circuits functional hold room stochastic temperature test timing ultra-low violation
表題 (title) Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature
表題 (英文)
著者名 (author) T. Nakayama,M. Hashimoto
英文著者名 (author) T. Nakayama,M. Hashimoto
キー (key) T. Nakayama,M. Hashimoto
定期刊行物名 (journal) IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
定期刊行物名 (英文)
巻数 (volume) 102-A
号数 (number) 7
ページ範囲 (pages) 914--917
刊行月 (month) 7
出版年 (year) 2019
Impact Factor (JCR)
URL
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル pdf (application/pdf) [一般閲覧可]
BiBTeXエントリ
@article{id497,
         title = {Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature},
        author = {T. Nakayama and M. Hashimoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {102-A},
        number = {7},
         pages = {914--917},
         month = {7},
          year = {2019},
}