Search: 簡易 | 詳細 || Language: 英語 | 日本語 || ログイン |

16 件の該当がありました. : このページのURL : HTML


論文誌
[1] T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, and M. Hashimoto, "Impact of Self-Heating in Wire Interconnection on Timing," IEICE Trans. on Electronics, volume E93-C, number 3, pages 388--392, March 2010. [136.pdf]
[2] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 2, pages 250--260, February 2010. [134.pdf]
[3] T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto, "An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3016--3023, December 2009. [129.pdf]
[4] A. Kurokawa, T. Sato, T. Kanamoto, and M. Hashimoto, "Interconnect Modeling: a Physical Design Perspective (Invited)," IEEE Transactions on Electron Devices, volume 56, number 9, pages 1840--1851, September 2009. [126.pdf]
[5] T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, "Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 92-A, number 4, pages 990--997, April 2009. [119.pdf]
[6] T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, and M. Hashimoto, "Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3666-3670, December 2006. [5.pdf]
[7] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]
[8] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜, "遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会論文誌, volume 44, number 5, pages 1301-1310, 2003年5月. [21.pdf]
国際会議
[1] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 47-53, November 2006. [22.pdf]
[2] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process Variations," In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 59-64, February 2006.
[3] T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, and M. Hashimoto, "Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 149-155, January 2003. [40.pdf]
国内会議(査読付き)
[1] 新開健一, 橋本昌宜, 黒川敦, 尾上孝雄, "電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル," 第19回 回路とシステム(軽井沢)ワークショップ, pages 559-564, 2006年4月. [75.pdf]
[2] 金本俊幾, 阿久津滋聖, 中林太美世, 一宮敬弘, 蜂屋孝太郎, 石川博, 室本栄, 小林宏行, 橋本昌宜, 黒川敦, "遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価," 情報処理学会DAシンポジウム, pages 265-270, 2004年7月.
[3] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会DAシンポジウム, pages 149-154, 2002年7月.
[4] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスが配線遅延に及ぼす影響の定量的評価方法," 第15回 回路とシステム(軽井沢)ワークショップ, pages 493-498, 2002年4月.
研究会・全国大会等
[1] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスに起因する配線遅延変動の統計的予測手法," 2002年電子情報通信学会ソサイエティ大会講演論文集, number TA-2-4, pages 247-248, 2002年9月.