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論文誌

[1] T. Okumura and M. Hashimoto, "Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 10, pages 1948--1953, October 2011. [164.pdf]

[2] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, "Gate Delay Estimation in STA under Dynamic Power Supply Noise," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2447--2455, December 2010. [151.pdf]

[3] T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, and M. Hashimoto, "Impact of Self-Heating in Wire Interconnection on Timing," IEICE Trans. on Electronics, volume E93-C, number 3, pages 388--392, March 2010. [136.pdf]

[4] T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto, "An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3016--3023, December 2009. [129.pdf]

[5] T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, "Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 92-A, number 4, pages 990--997, April 2009. [119.pdf]

[6] H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, and M. Hashimoto, "Proposal of Metrics for SSTA Accuracy Evaluation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 4, pages 808--814, April 2007. [81.pdf]

国際会議

[1] T. Okumura and M. Hashimoto, "Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2010. [147.pdf]

[2] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, "Gate Delay Estimation in STA under Dynamic Power Supply Noise," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 775 -- 780, January 2010. [132.pdf]