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論文誌

[1] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, "Gate Delay Estimation in STA under Dynamic Power Supply Noise," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2447--2455, December 2010. [151.pdf]

[2] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 4, 541 - 553, April 2009. [118.pdf]

国際会議

[1] J. Chen and M. Hashimoto, "A Frequency-Dependent Target Impedance Method Fulfilling both Average and Dynamic Voltage Drop Constraints," Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), June 2019. [pdf]

[2] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, "Gate Delay Estimation in STA under Dynamic Power Supply Noise," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 775 -- 780, January 2010. [132.pdf]

[3] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 107--108, January 2008. [97.pdf]