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20 件の該当がありました． : このページのURL : HTML

論文誌

[1] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Supply Noise Suppression by Triple-Well Structure," IEEE Transactions on VLSI Systems, volume 21, number 4, pages 781--785, April 2013. [169.pdf]

[2] Y. Ogasahara, M. Hashimoto, and T. Onoye, "All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform," IEEE Journal of Solid-State Circuits, volume 44, number 6, pages 1745--1755, June 2009. [124.pdf]

[3] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3461-3464, December 2008. [111.pdf]

[4] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects," IEEE Journal of Solid-State Circuits, volume 43, number 3, pages 718--728, March 2008. [99.pdf]

[5] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Transactions on Circuits and Systems II, volume 54, number 10, pages 868--872, October 2007. [94.pdf]

[6] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 4, pages 724--731, April 2007. [80.pdf]

国際会議

[1] Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to SSO," Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 19--20, May 2010. [139.pdf]

[2] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 397--400, November 2008. [109.pdf]

[3] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 107--108, January 2008. [97.pdf]

[4] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," Proceedings of 37th European Solid-State Device Research Conference (ESSDERC), pages 115--118, September 2007. [92.pdf]

[5] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 783--786, September 2007. [90.pdf]

[6] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects," In Proceedings of IEEE International Conference on Computer Design (ICCD), pages 70-75, October 2006. [23.pdf]

[7] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 721-724, September 2006. [24.pdf]

[8] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC),, pages 861-864, September 2006. [25.pdf]

[9] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Delay Variation Due to Inductive Coupling," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 305-308, September 2005. [26.pdf]

国内会議(査読付き)

[1] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測," 第19回 回路とシステム(軽井沢)ワークショップ, pages 5-10, 2006年4月. [73.pdf]

研究会・全国大会等

[1] 小笠原泰弘, 榎並孝司, 橋本昌宜, 佐藤高史、尾上孝雄, "電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現," 電子情報通信学会 集積回路研究会,, number ICD2006-174, 2007年1月.

[2] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測," 電子情報通信学会 集積回路研究会, number ICD2006-173, 2007年1月.

[3] 小笠原泰弘, 新開健一, 榎並孝司, 阿部慎也, 二宮進有, 橋本昌宜, "ナノメートル世代のVLSIタイミング設計技術の研究," 第10回システムLSIワークショップ, pages 195-198, 2006年11月.

[4] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "誘導性・容量性クロストークノイズによる遅延変動の測定と評価," 電子情報通信学会 集積回路研究会, number ICD2005-74, 2005年8月.