List of works
この検索内の頻出タグ: model:9 voltage:3 analysis:2 considering:2 dependence:2 dnn:2 fault:2 injections:2 interdependency:2 load:2 on-chip:2 parameters:2 pdn:2 supply:2 vulnerability:2 3d:1 all:1 application-level:1 average:1 bulk:1 chip:1 clock:1 constructing:1 construction:1 counter:1 cpu:1 cross:1 current:1 delay:1 drop:1
- 論文誌
- [1] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Vulnerability Estimation of DNN Model Parameters with Few Fault Injections," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E106-A, number 3, pages 523-531, March 2023. [pdf]
- [2] J. Chen, H. Kando, T. Kanamoto, C. Zhuo, and M. Hashimoto, "A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions," IEEE Transactions on Components, Packaging and Manufacturing Technology, volume 9, number 9, pages 1669--1679, September 2019. [pdf]
- [3] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Transactions on Circuits and Systems II, volume 54, number 10, pages 868--872, October 2007. [94.pdf]
- 国際会議
- [1] K. Takeuchi, T. Kato, and M. Hashimoto, "An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs," Proceedings of International Symposium on Reliability Physics (IRPS), April 2024. [pdf]
- [2] K. Ito, H. Itsuji, T. Uezono, T. Toba, M. Itoh, and M. Hashimoto, "Constructing Application-Level GPU Error Rate Model with Neutron Irradiation Experiment," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022.
- [3] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections," Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 60-63, March 2022. [pdf]
- [4] T. Tanaka, M. Hashimoto, and Y. Takeuchi, "Linear Programming Based Reliable Software Performance Model Construction with Noisy CPU Performance Counter Values," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), March 2021.
- [5] J. Chen, T. Kanamoto, H. Kando, and M. Hashimoto, "An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency," Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), May 2018. [pdf]
- [6] K. Hirosue, S. Ukawa, Y. Itoh, T. Onoye, and M. Hashimoto, "GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction," Proceedings of International Conference on Intelligent User Interfaces (IUI), pages 173--178, March 2017. [pdf]