Academic Journal
|
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye
|
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement
|
IEEE Transactions on Circuits and Systems II
| 54(10)
|
868--872
|
October 2007
|
| 94.pdf
|
Academic Journal
|
T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto
|
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E88-A(12)
|
3382-3389
|
December 2005
|
| 9.pdf
|
Academic Journal
|
A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, H. Masuda
|
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E88-A(12)
|
3453-3462
|
December 2005
|
| 10.pdf
|
International Conference
|
, , , , , , , , , , M. Hashimoto
|
A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --
|
Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
|
|
|
August 2025
|
| pdf
|
International Conference
|
J. Chen, T. Kanamoto, H. Kando, M. Hashimoto
|
An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency
|
Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)
|
|
|
May 2018
|
| pdf
|
International Conference
|
Y. Takai, Y. Ogasahara, M. Hashimoto, T. Onoye
|
Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to SSO
|
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)
|
|
19--20
|
May 2010
|
| 139.pdf
|
International Conference
|
T. Sato, N. Ono, J. Ichimiya, K. Hachiya, M. Hashimoto
|
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
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1074-1077
|
January 2005
|
| 34.pdf
|
International Conference
|
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
|
Performance Prediction of On-Chip Global Signaling
|
IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)
|
|
87-100
|
November 2004
|
|
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International Conference
|
A. Muramatsu, M. Hashimoto, H. Onodera
|
LSI Power Network Analysis with On-Chip Wire Inductance
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
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55-60
|
October 2004
|
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