この検索内の頻出タグ: on-chip^:8 analysis^:4 supply^:3 delay^:2 design^:2 flattening^:2 gradient^:2 measurement^:2 model^:2 noise^:2 power^:2 soc^:2 temperature^:2 thermal^:2 voltage^:2 average^:1 capacitance^:1 clock^:1 considering^:1 correlation^:1 current^:1 dependence^:1 drop^:1 due^:1 expressions^:1 full-chip^:1 global^:1 i/o^:1 increase^:1 inductance^:1

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論文誌

[1] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Transactions on Circuits and Systems II, volume 54, number 10, pages 868--872, October 2007. [94.pdf]

[2] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3382-3389, December 2005. [9.pdf]

[3] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]

国際会議

[1] J. Chen, T. Kanamoto, H. Kando, and M. Hashimoto, "An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency," Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), May 2018. [pdf]

[2] Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to SSO," Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 19--20, May 2010. [139.pdf]

[3] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1074-1077, January 2005. [34.pdf]

[4] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip Global Signaling," In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), pages 87-100, November 2004.

[5] A. Muramatsu, M. Hashimoto, and H. Onodera, "LSI Power Network Analysis with On-Chip Wire Inductance," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 55-60, October 2004.