この検索内の頻出タグ: data^:3 accelerators^:1 access^:1 algorithms^:1 allocation^:1 architecture^:1 bank^:1 edge-ai^:1 external^:1 layer-wise^:1 locking^:1 logic^:1 memory^:1 multi-path^:1 networks^:1 neural^:1 on-chip^:1 over^:1 reduction^:1 refresh^:1 rolling^:1 scalable^:1 securing^:1 storage^:1 support^:1 tfhe^:1 training^:1 user^:1 vectors^:1

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国際会議

[1] Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, "A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 採録済.

[2] K. Suemitsu, K. Matsuoka, T. Sato, and M. Hashimoto, "Logic Locking Over TFHE for Securing User Data and Algorithms," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2024. [pdf]

[3] T. Tanio, J. Yu, and M. Hashimoto, "Training Data Reduction Using Support Vectors for Neural Networks," Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC), November 2019. [pdf]