この検索内の頻出タグ: data^:4 tfhe^:2 accelerators^:1 access^:1 algorithms^:1 allocation^:1 architecture^:1 bank^:1 computations^:1 corruption^:1 detection^:1 edge-ai^:1 error^:1 evaluation^:1 external^:1 gpus^:1 layer-wise^:1 locking^:1 logic^:1 memory^:1 multi-path^:1 networks^:1 neural^:1 on-chip^:1 over^:1 rate^:1 reduction^:1 refresh^:1 reliable^:1 rolling^:1

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論文誌

[1] Masakazu Yoshida, Kotaro Matsuoka, and Masanori Hashimoto, "Soft Error Rate Evaluation and Silent Data Corruption Detection for Reliable TFHE Computations on GPUs," IEEE Transactions on Dependable and Secure Computing, 採録済.

国際会議

[1] Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, "A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2025. [pdf]

[2] K. Suemitsu, K. Matsuoka, T. Sato, and M. Hashimoto, "Logic Locking Over TFHE for Securing User Data and Algorithms," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2024. [pdf]

[3] T. Tanio, J. Yu, and M. Hashimoto, "Training Data Reduction Using Support Vectors for Neural Networks," Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC), November 2019. [pdf]