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論文誌

[1] Q. Cheng, M. Huang, C. Man, A. Shen, L. Dai, H. Yu, and M. Hashimoto, "Reliability Exploration of System-On-Chip with Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, volume 70, number 10, 3978 -- 3991, October 2023. [pdf]

[2] Q. Cheng, L. Dai, M. Huang, A. Shen, W. Mao, M. Hashimoto, and H. Yu, "A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier," IEEE Transactions on Circuits and Systems II, volume 70, number 6, 2246 - 2250, June 2023. [pdf]

[3] G. L. Zhang, B. Li, X. Huang, X. Yin, C. Zhuo, M. Hashimoto, and U. Schlichtmann, "Virtualsync+: Timing Optimization with Virtual Synchronization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 41, number 12, pages 5526-5540, December 2022. [pdf]

[4] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 2, pages 250--260, February 2010. [134.pdf]

[5] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]