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Q. Cheng, L. Dai, M. Huang, A. Shen, W. Mao, M. Hashimoto, and H. Yu, "A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier," IEEE Transactions on Circuits and Systems II, 70(6), 2246 - 2250, June 2023.
ID 608
分類 論文誌
タグ accelerator booth convolutional low-power multiplier network neural pre-encoding radix-4 sparse
表題 (title) A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier
表題 (英文)
著者名 (author) Q. Cheng,L. Dai,M. Huang,A. Shen,W. Mao,M. Hashimoto,H. Yu
英文著者名 (author) ,,,,,M. Hashimoto,
キー (key) ,,,,,M. Hashimoto,
定期刊行物名 (journal) IEEE Transactions on Circuits and Systems II
定期刊行物名 (英文)
巻数 (volume) 70
号数 (number) 6
ページ範囲 (pages) 2246 - 2250
刊行月 (month) 6
出版年 (year) 2023
Impact Factor (JCR)
URL
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル pdf (application/pdf) [一般閲覧可]
BiBTeXエントリ
@article{id608,
         title = {A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier},
        author = {Q. Cheng and L. Dai and M. Huang and A. Shen and W. Mao and M. Hashimoto and H. Yu},
       journal = {IEEE Transactions on Circuits and Systems II},
        volume = {70},
        number = {6},
         pages = {2246 - 2250},
         month = {6},
          year = {2023},
}