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論文誌
[1] G. L. Zhang, B. Li, X. Huang, X. Yin, C. Zhuo, M. Hashimoto, and U. Schlichtmann, "Virtualsync+: Timing Optimization with Virtual Synchronization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 41, number 12, pages 5526-5540, December 2022. [pdf]
[2] B. Li, M. Hashimoto, and U. Schlichtmann, "From Process Variations to Reliability: a Survey of Timing of Digital Circuits in the Nanometer Era (Invited)," IPSJ Transactions on System LSI Design Methodology, volume 11, pages 2--15, February 2018.
国際会議
[1] L. Zhang, B. Li, and M. Hashimoto. U. Schlichtmann, "VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units," Proceedings of Design Automation Conference (DAC), June 2018. [pdf]
[2] H.-Y. Su, B.-S. Wang, S.-Y. Hsieh, Y.-L. Li, I-H. Wu, C.-C. Wu, W.-C. Shih, H. Onodera, and M. Hashimoto, "Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2016.
[3] U. Schlichtmann, M. Hashimoto, I. H.-R. Jiang, and B. Li, "Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits (Invited)," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 705--711, January 2016. [227.pdf]