この検索内の頻出タグ: network^:8 neural^:7 multiplier^:3 training^:3 accelerator^:2 bayesian^:2 efficient^:2 floating-point^:2 fpga^:2 logarithm-approximate^{:2 :1} activations^:1 analysis^:1 applicable^:1 b2n2^:1 bernoulli^:1 booth^:1 bynqnet^:1 convolutional^:1 energy^:1 estimation^:1 imager^:1 inductance^:1 is^:1 lookup-table-based^:1 low-power^:1 lsi^:1 memory^:1 minimizing^:1 neuromorphic^:1

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論文誌

[1] Q. Cheng, L. Dai, M. Huang, A. Shen, W. Mao, M. Hashimoto, and H. Yu, "A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier," IEEE Transactions on Circuits and Systems II, volume 70, number 6, 2246 - 2250, June 2023. [pdf]

[2] H. Awano and M. Hashimoto, "B2N2: Resource Efficient Bayesian Neural Network Accelerator Using Bernoulli Sampler on FPGA," Integration, the VLSI Journal, volume 89, pages 1-8, March 2023. [pdf]

[3] T. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, "Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training," Integration, the VLSI Journal, volume 74, pages 19--31, September 2020. [pdf]

国際会議

[1] Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics," Digest of Symposium on VLSI Technology and Circuits, 採録済.

[2] K. Onishi, J. Yu, and M. Hashimoto, "Memory Efficient Training Using Lookup-Table-Based Quantization for Neural Network," Proceedings of International Conference on Artificial Intelligence Circuits and Systems (AICAS), August 2020. [pdf]

[3] H. Awano and M. Hashimoto, "BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA," Proceedings of Design, Automation and Test in Europe Conference (DATE), April 2020. [pdf]

[4] T.-Y. Cheng, J. Yu, and M. Hashimoto, "Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier," Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), July 2019. [pdf]

[5] A. Muramatsu, M. Hashimoto, and H. Onodera, "LSI Power Network Analysis with On-Chip Wire Inductance," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 55-60, October 2004.