この検索内の頻出タグ: energy^:9 activation-aware^:3 assignment^:3 dnn^:3 minimization^:3 mode-wise^:3 multiplier^:3 slack^:3 8-bit^:2 accelerators^:2 design^:2 inference^:2 input^:2 minimizing^:2 scaling^:2 segmentation^:2 squeezing^:2 training^:2 voltage^:2 voltage-scalable^:2 adaptive^:1 bit-width^:1 capture^:1 charged^:1 emitted^:1 floating-point^:1 following^:1 fpga^:1 implementation^:1 keyword^:1

9 件の該当がありました． : このページのURL : HTML

論文誌

[1] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E105-A, number 3, pages 497--508, March 2022. [pdf]

国際会議

[1] Soshi Ishitani, Shoichiro Kawase, Haruto Shimojo, Haruto Yoshikawa, Marie Mori, Yukinobu Watanabe, Megumi Niikura, Rurie Mizuno, Teiichiro Matsuzaki, Yuji Yamaguchi, Dai Tomono, Keisuke Yokota, Shunsuke Asari, Katsuhiko Ishida, Masanori Hashimoto, Yuibi Gomi, and Futoshi Minato, "Energy Spectra of Light Charged Particles Emitted Following Muon Nuclear Capture on Natcu," The 8th international workshop on Compound-Nuclear Reactions and Related Topics 2026 (CNR*26), 採録済.

[2] Y. Tada, M. Hashimoto, M. Miyamura, X. Bai, T. Sakamoto, and H. Ochi, "Memory and Energy Savings in the FPGA Implementation of Keyword Spotting with Stream Processing," Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS), October 2025.

[3] M. Zhang and M. Hashimoto, "Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators," International collaboration Symposium on Information, Production and Systems (ISIPS), November 2024.

[4] T. Cheng and M. Hashimoto, "Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2021. [pdf]

[5] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 284 -- 290, January 2021. [pdf]

[6] T.-Y. Cheng, J. Yu, and M. Hashimoto, "Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier," Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), July 2019. [pdf]

国内会議(査読付き)

[1] Zhang Mingtao, Cheng Quan, 粟野 皓光, Lin Longyang, 橋本 昌宜, "Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators," 情報処理学会DAシンポジウム, 2024年.

研究会・全国大会等

[1] T.-Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," 電子情報通信学会 VLSI設計技術研究会, March 2021.