
- 論文誌
- [1] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E105-A, number 3, pages 497--508, March 2022. [pdf]
- 国際会議
- [1] M. Zhang and M. Hashimoto, "Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators," International collaboration Symposium on Information, Production and Systems (ISIPS), November 2024.
- [2] T. Cheng and M. Hashimoto, "Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2021. [pdf]
- [3] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 284 -- 290, January 2021. [pdf]
- [4] T.-Y. Cheng, J. Yu, and M. Hashimoto, "Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier," Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), July 2019. [pdf]
- 国内会議(査読付き)
- [1] Zhang Mingtao, Cheng Quan, 粟野 皓光, Lin Longyang, 橋本 昌宜, "Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators," 情報処理学会DAシンポジウム, 2024年.
- 研究会・全国大会等
- [1] T.-Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," 電子情報通信学会 VLSI設計技術研究会, March 2021.