- 論文誌
- [1] M. Hashimoto, H. Onodera, and K. Tamaru, "A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E82-A, number 1, pages 159-166, January 1999. [19.pdf]
- 国際会議
- [1] M. Zhang and M. Hashimoto, "Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators," International collaboration Symposium on Information, Production and Systems (ISIPS), November 2024.
- 国内会議(査読付き)
- [1] Zhang Mingtao, Cheng Quan, 粟野 皓光, Lin Longyang, 橋本 昌宜, "Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators," 情報処理学会DAシンポジウム, 2024年.