: M. Hashimoto, H. Onodera, and K. Tamaru, A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits, January 1999.
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| M. Hashimoto, H. Onodera, and K. Tamaru, "A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E82-A(1), pp. 159-166, January 1999. | |
| ID | 28 |
| 分類 | 論文誌 |
| タグ | cell-based circuits cmos delay input method optimization power reordering |
| 表題 (title) |
A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits |
| 表題 (英文) |
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| 著者名 (author) |
M. Hashimoto,H. Onodera,K. Tamaru |
| 英文著者名 (author) |
M. Hashimoto,H. Onodera,K. Tamaru |
| キー (key) |
M. Hashimoto,H. Onodera,K. Tamaru |
| 定期刊行物名 (journal) |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences |
| 定期刊行物名 (英文) |
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| 巻数 (volume) |
E82-A |
| 号数 (number) |
1 |
| ページ範囲 (pages) |
159-166 |
| 刊行月 (month) |
1 |
| 出版年 (year) |
1999 |
| Impact Factor (JCR) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 19.pdf (application/pdf) [一般閲覧可] |
| BiBTeXエントリ |
@article{id28,
title = {A Power and Delay Optimization Method using Input Reordering in Cell-Based {CMOS} Circuits},
author = {M. Hashimoto and H. Onodera and K. Tamaru},
journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
volume = {E82-A},
number = {1},
pages = {159-166},
month = {1},
year = {1999},
}
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