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\title{\LARGE\bf 研究業績リスト}

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\section{論文誌}
\label{sec:0}

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\begin{enumerate}
\item
Y. Masuda, T. Onoye, and M. Hashimoto, ``Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving,'' IEEE Transactions on VLSI Systems, volume 26, number 11, pages 2217--2229, November 2018.
\item
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, ``Gate Delay Estimation in {STA} under Dynamic Power  Supply Noise,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2447--2455, December 2010.
\item
T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter  and Skew Due to Power Supply Noise and Process  Variation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2399--2408, December 2010.
\item
T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 4, 541 - 553, April 2009.
\item
M. Hashimoto, H. Onodera, and K. Tamaru, ``A Power and Delay Optimization Method Using Input Reordering in Cell-Based {CMOS} Circuits,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E82-A, number 1, pages 159-166, January 1999.
\end{enumerate}
\section{国際会議}
\label{sec:1}

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\begin{enumerate}
\item
M. Hashimoto and J. Chen, ``Proactive Supply Noise Mitigation and Design Methodology for Robust {VLSI} Power Distribution (Invited),'' Proceedings of China Semiconductor Technology International Conference (CSTIC),   March 2021.
\item
J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, and Y. Momiyama, ``Activation-Aware Slack Assignment {(ASA)} for Mode-Wise Power Saving in High-End {ISP},'' Design Automation Conference, Designer/IP Track,   June 2019.
\item
R. Shirai, T. Hirose, and M. Hashimoto, ``A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes,'' Proceedings of International NEWCAS Conference,  pages 152--156, June 2018.
\item
R. Shirai, T. Hirose, and M. Hashimoto, ``Dedicated Antenna Less Power Efficient {OOK} Transmitter for {mm-Cubic} {IoT} Nodes,'' Proceedings of European Microwave Conference (EuMC),  pages 101--104, October 2017.
\item
S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, ``Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices,'' Proceedings of IEEE Wireless Power Transfer Conference (WPTC),   May 2017.
\item
S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, ``Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes,'' Proceedings of International Symposium on Antennas and Propagation (ISAP),   October 2016.
\item
Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to {SSO},'' Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI),  pages 19--20, May 2010.
\item
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, ``Gate Delay Estimation in {STA} under Dynamic Power Supply Noise,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC),  775 -- 780, January 2010.
\item
Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site {SoC} Power Integrity Verification,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC),  pages 107--108, January 2008.
\item
A. Muramatsu, M. Hashimoto, and H. Onodera, ``{LSI} Power Network Analysis with On-Chip Wire Inductance,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI),  pages 55-60, October 2004.
\item
T. Sato, M. Hashimoto, and H. Onodera, ``An {IR-drop} Minimization by Optimizing Number and Location of Power Supply Pads,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI),  pages 66-72, October 2004.
\end{enumerate}
\section{著書}
\label{sec:4}

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\item
R. Nair, M. Hashimoto, and N. Srivastava, ``{IC} Power Integrity and Optimal Power Delivery,'' Book chapter, Power Integrity Analysis and Management for Integrated Circuits, Prentice Hall PTR,   May 2010.
\end{enumerate}
以上．
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