この検索内の頻出タグ: design^:9 voltage^:7 activation-aware^:5 assignment^:5 scaling^:5 slack^:5 methodology^:4 mode-wise^:4 power^:4 bit-width^:3 critical^:3 energy^:3 error^:3 isolation^:3 minimization^:3 mttf-aware^:3 over-scalable^:3 path^:3 timing^:3 adaptively^:2 circuit^:2 performance^:2 saving^:2 small^:2 voltage-scalable^:2 wireless^:2 adaptation^:1 adaptive^:1 applicable^:1 are^:1

23 件の該当がありました． : このページのURL : HTML

論文誌

[1] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E105-A, number 3, pages 497--508, March 2022. [pdf]

[2] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , and M. Hashimoto, "Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 105-A, number 3, pages 509--517, March 2022. [pdf]

[3] T. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, "Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training," Integration, the VLSI Journal, volume 74, pages 19--31, September 2020. [pdf]

[4] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 102-A, number 7, pages 867--877, July 2019. [pdf]

[5] Y. Masuda, T. Onoye, and M. Hashimoto, "Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving," IEEE Transactions on VLSI Systems, volume 26, number 11, pages 2217--2229, November 2018. [pdf]

[6] Y. Masuda, T. Onoye, and M. Hashimoto, "Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E100-A, number 7, pages 1452--1463, July 2017. [pdf]

[7] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]

国際会議

[1] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design," Proceedings of Design, Automation and Test in Europe Conference (DATE), February 2021. [pdf]

[2] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 284 -- 290, January 2021. [pdf]

[3] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling," International Workshop on Logic and Synthesis (IWLS), July 2020.

[4] J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, and Y. Momiyama, "Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP," Design Automation Conference, Designer/IP Track, June 2019.

[5] Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, and M. Hashimoto, "Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2018. [pdf]

[6] M. Hashimoto and Y. Masuda, "MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2018. [pdf]

[7] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018. [pdf]

[8] S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, "Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices," Proceedings of IEEE Wireless Power Transfer Conference (WPTC), May 2017. [pdf]

[9] Y. Masuda, M. Hashimoto, and T. Onoye, "Critical Path Isolation for Time-To-Failure Extension and Lower Voltage Operation," Proceedings of International Conference on Computer-Aided Design (ICCAD), November 2016. [230.pdf]

[10] Y. Akihara, T. Hirose, S. Masuda, N. Kuroki, M. Numa, and M. Hashimoto, "Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems," Proceedings of International Symposium on Antennas and Propagation (ISAP), October 2016. [232.pdf]

[11] S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, "Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes," Proceedings of International Symposium on Antennas and Propagation (ISAP), October 2016. [pdf]

[12] Y. Masuda, M. Hashimoto, and T. Onoye, "Hardware-Simulation Correlation of Timing Error Detection Performance of Software-Based Error Detection Mechanisms," Proceedings of International On-Line Testing Symposium (IOLTS), pages 84--89, July 2016. [228.pdf]

[13] Y. Masuda, M. Hashimoto, and T. Onoye, "Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.

[14] Y. Masuda, M. Hashimoto, and T. Onoye, "Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise," Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 315-322, November 2015. [224.pdf]

[15] S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, "Stochastic Timing Error Rate Estimation under Process and Temporal Variations," Proceedings of International Test Conference (ITC), October 2015. [223.pdf]

研究会・全国大会等

[1] T.-Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," 電子情報通信学会 VLSI設計技術研究会, March 2021.