: Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling, July 2020.
Detail of a work
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| Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling," International Workshop on Logic and Synthesis (IWLS), July 2020. | |
| ID | 550 |
| 分類 | 国際会議 |
| タグ | bit-width critical design isolation over-scalable path scaling variation-tolerant voltage |
| 表題 (title) |
Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling |
| 表題 (英文) |
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| 著者名 (author) |
Y. Masuda,J. Nagayama,T. Cheng,T. Ishihara,Y. Momiyama,M. Hashimoto |
| 英文著者名 (author) |
Y. Masuda,,,,,M. Hashimoto |
| キー (key) |
Y. Masuda,,,,,M. Hashimoto |
| 定期刊行物名 (journal) |
International Workshop on Logic and Synthesis (IWLS) |
| 定期刊行物名 (英文) |
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| 巻数 (volume) |
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| 号数 (number) |
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| ページ範囲 (pages) |
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| 刊行月 (month) |
7 |
| 出版年 (year) |
2020 |
| Impact Factor (JCR) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 利用できません． |
| BiBTeXエントリ |
@article{id550,
title = {Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling},
author = {Y. Masuda and J. Nagayama and T. Cheng and T. Ishihara and Y. Momiyama and M. Hashimoto},
journal = {International Workshop on Logic and Synthesis (IWLS)},
month = {7},
year = {2020},
}
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