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T. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, "Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training," Integration, the VLSI Journal, 74, pp. 19--31, September 2020.
ID 548
分類 論文誌
タグ applicable floating-point is logarithm-approximate multiplier network neural power-efficient training
表題 (title) Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training
表題 (英文)
著者名 (author) T. Cheng,Y. Masuda,J. Chen,J. Yu,M. Hashimoto
英文著者名 (author) ,Y. Masuda,J. Chen,J. Yu,M. Hashimoto
キー (key) ,Y. Masuda,J. Chen,J. Yu,M. Hashimoto
定期刊行物名 (journal) Integration, the VLSI Journal
定期刊行物名 (英文)
巻数 (volume) 74
号数 (number)
ページ範囲 (pages) 19--31
刊行月 (month) 9
出版年 (year) 2020
Impact Factor (JCR)
URL
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル pdf (application/pdf) [一般閲覧可]
BiBTeXエントリ
@article{id548,
         title = {Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training},
        author = {T. Cheng and Y. Masuda and J. Chen and J. Yu and M. Hashimoto},
       journal = {Integration, the VLSI Journal},
        volume = {74},
         pages = {19--31},
         month = {9},
          year = {2020},
}