Table of works
Frequent tags in this search: scaling:7 voltage:6 bit-width:4 design:4 critical:3 isolation:3 over-scalable:3 path:3 adaptive:2 energy:2 methodology:2 activation-aware:1 are:1 assignment:1 bulk:1 circuit:1 cmos:1 compatible:1 contribution:1 dnn:1 ff:1 highly:1 invited:1 low-power:1 minimization:1 minimizing:1 mode-wise:1 mttf-aware:1 processor:1 rate:1
7 publications are found. : URL for this page. : HTML
| Author (author) | Title (title) | Journal/Conference | Volume / Number | Pages (pages) | Published date | Impact factor / Acceptance | File | |
|---|---|---|---|---|---|---|---|---|
| Academic Journal |
, Y. Masuda, , , J. Chen, M. Hashimoto |
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences | E105-A(3) |
497--508 |
March 2022 |
pdf | |
| Academic Journal |
, M. Hashimoto |
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences | 105-A(3) |
509--517 |
March 2022 |
pdf | |
| International Conference |
, M. Hashimoto |
Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling |
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) | May 2021 |
pdf | |||
| International Conference |
Y. Masuda, , , , , M. Hashimoto |
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design |
Proceedings of Design, Automation and Test in Europe Conference (DATE) | February 2021 |
pdf | |||
| International Conference |
Y. Masuda, , , , , M. Hashimoto |
Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling |
International Workshop on Logic and Synthesis (IWLS) | July 2020 |
||||
| International Conference |
M. Hashimoto, Y. Masuda |
MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited) |
Proceedings of China Semiconductor Technology International Conference (CSTIC) | March 2018 |
pdf | |||
| International Conference |
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto |
Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology |
IEEE Nuclear and Space Radiation Effects Conference (NSREC) | July 2013 |