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8 件の該当がありました. : このページのURL : HTML


論文誌
[1] M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, and Y. Watanabe, "Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation (Invited)," Integration, the VLSI Journal, volume 69, pages 161--179, November 2019. [pdf]
[2] B. Li, M. Hashimoto, and U. Schlichtmann, "From Process Variations to Reliability: a Survey of Timing of Digital Circuits in the Nanometer Era (Invited)," IPSJ Transactions on System LSI Design Methodology, volume 11, pages 2--15, February 2018.
国際会議
[1] M. Hashimoto and J. Chen, "Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2021. [pdf]
[2] M. Hashimoto, Y. Nakazawa, R. Doi, and J. Yu, "Interconnect Delay Analysis for RRAM Crossbar Based FPGA (Invited)," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018. [pdf]
[3] M. Hashimoto and Y. Masuda, "MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2018. [pdf]
[4] M. Hashimoto, R. Shirai, Y. Itoh, and T. Hirose, "Toward Real-Time 3D Modeling System with Cubic-Millimeters Wireless Sensor Nodes (Invited)," Proceedings of IEEE International Conference on ASIC, pages 1087--1091, October 2017. [pdf]
[5] M. Hashimoto, W. Liao, and S. Hirokawa, "Soft Error Rate Estimation with TCAD and Machine Learning (Invited)," Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2017. [pdf]
[6] M. Hashimoto, "Soft Error Immunity of Subthreshold SRAM (Invited)," Proceedings of IEEE International Conference on ASIC, pages 91--94, October 2013. [192.pdf]