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論文誌

[1] M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, and Y. Watanabe, "Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation (Invited)," Integration, the VLSI Journal, volume 69, pages 161--179, November 2019. [pdf]

[2] W. Liao and M. Hashimoto, "Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate," IEICE Trans. on Electronics, volume E102-C, number 4, pages 296--302, April 2019. [pdf]

[3] H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM," IEEE Transactions on Device and Materials Reliability, volume 14, number 1, 463 -- 470, March 2014. [185.pdf]

[4] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, volume 58, number 4, pages 2097--2102, August 2011. [159.pdf]

国際会議

[1] Q. Cheng, Q. Li, L. Lin, W. Liao, L. Dai, H. Yu, and M. Hashimoto, "How Accurately Can Soft Error Impact Be Estimated in Black-Box/White-Box Cases? -- a Case Study with an Edge AI SoC --," Proceedings of Design Automation Conference (DAC), 採録済.

[2] M. Niikura, R. Mizuno, S. Manabe, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, A. Hillier, N. Kawamura, Y. Kawashima, S. Kawase, T. Kawata, K. Kitafuji, F. Minato, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, M. Tampo, D. Tomono, I. Umegaki, Y. Yamaguchi, and Y. Watanabe, "Nuclear Physics for Muon-Induced Soft Error," Workshop for Computational Technique for Negative Muon Spectroscopy and Elemental Analysis, August 2023.

[3] R. Iwamoto and M. Hashimoto, "Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication," Proceedings of International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2023. [pdf]

[4] M. Harimaya, R. Shirai, and M. Hashimoto, "Toward Instant 3D Modeling: Highly Parallelizable Shape Reproduction Method for Soft Object Containing Numerous Tiny Position Trackers," Proceedings of International Conference on Intelligent User Interfaces (IUI), March 2023. [pdf]

[5] M. Hashimoto and W. Liao, "Soft Error and Its Countermeasures in Terrestrial Environment," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2020. [pdf]

[6] M. Hashimoto, W. Liao, S. Manabe, and Y. Watanabe, "Characterizing Soft Error Rates of 65-nm SOTB and Bulk SRAMs with Muon and Neutron Beams (Invited)," Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2018. [pdf]

[7] K. Itoh, J. Yu, and M. Hashimoto, "Adapting Soft Cascade to Mac Operations of Convolutional Neural Networks," Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC), August 2018.

[8] M. Hashimoto, W. Liao, and S. Hirokawa, "Soft Error Rate Estimation with TCAD and Machine Learning (Invited)," Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2017. [pdf]

[9] W. Liao, S. Hirokawa, R. Harada, and M. Hashimoto, "Contributions of SRAM, FF and Combinational Circuit to Chip-Level Neutron-Induced Soft Error Rate -- Bulk vs. FD-SOI at 0.5 and 1.0V --," Proceedings of International NEWCAS Conference, pages 33-37, June 2017. [pdf]

[10] S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, and M. Hashimoto, "Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2016. [pdf]

[11] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 nm Bulk CMOS," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]

[12] M. Hashimoto, "Soft Error Immunity of Subthreshold SRAM (Invited)," Proceedings of IEEE International Conference on ASIC, pages 91--94, October 2013. [192.pdf]

[13] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," Proceedings of International Reliability Physics Symposium (IRPS), pages 213--217, May 2010. [140.PDF]

[14] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Soft Error Resilient VLSI Architecture for Signal Processing," Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 183--186, December 2009. [142.pdf]

著書

[1] E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M. Hashimoto, T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, and M. Sugihara, "Radiation-Induced Soft Errors," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.