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W. Liao and M. Hashimoto, "Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate," IEICE Trans. on Electronics, E102-C(4), pp. 296--302, April 2019. | |
ID | 501 |
分類 | 論文誌 |
タグ | analyzing chip-level circuit combinational error ff impacts neutron-induced rate soft sram |
表題 (title) |
Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate |
表題 (英文) |
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著者名 (author) |
W. Liao,M. Hashimoto |
英文著者名 (author) |
W. Liao,M. Hashimoto |
キー (key) |
W. Liao,M. Hashimoto |
定期刊行物名 (journal) |
IEICE Trans. on Electronics |
定期刊行物名 (英文) |
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巻数 (volume) |
E102-C |
号数 (number) |
4 |
ページ範囲 (pages) |
296--302 |
刊行月 (month) |
4 |
出版年 (year) |
2019 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id501, title = {Analyzing Impacts of {SRAM}, {FF} and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate}, author = {W. Liao and M. Hashimoto}, journal = {IEICE Trans. on Electronics}, volume = {E102-C}, number = {4}, pages = {296--302}, month = {4}, year = {2019}, } |